Streaming Fabric Interface with Separate Header and Payload Channels
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Solution Overview
Problem
Existing interconnect architectures in computing systems face challenges in efficiently handling high data rates and scalability, particularly in systems with multiple processors and cores, leading to increased complexity and latency in communication between devices.
Innovation Solution
A scalable streaming interface (SFI) is introduced that bifurcates header and data packets into separate physical channels, allowing for independent processing and reducing latency by enabling header processing while data is still streaming, and supports multiple protocols like PCIe and CXL.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect communication, then electrical communication is simplified, but communication speed and data rate capability are limited
Solution Approach 1:
The interconnect architecture is segmented into multiple point-to-point lanes instead of a single multi-drop bus. Each lane operates independently at high speed, allowing parallel communication between device pairs. This segmentation enables higher aggregate bandwidth while maintaining electrical simplicity in each individual lane.
Solution Approach 2:
The architecture transitions from a one-dimensional multi-drop bus topology to a multi-dimensional point-to-point mesh topology. This dimensional change allows communication to occur simultaneously along multiple independent paths, dramatically increasing communication capacity and flexibility without proportionally increasing complexity.
2Power
If multiple physical processors and cores are added to increase computing power, then processing capability is improved, but communication latency and complexity between devices increase
Solution Approach 1:
Headers are processed and validated in advance before the associated data payload arrives. The receiver decodes header information, performs error checking, and prepares buffer allocations while data is still being transmitted. This preliminary processing reduces the time required to handle complete data frames, lowering effective communication latency.
Solution Approach 2:
The interface maintains continuous operation by overlapping header processing with data reception. While data streams through the physical lanes, the receiver simultaneously processes headers from subsequent packets, ensuring that processing resources remain continuously utilized without idle waiting periods, thereby reducing average latency.
3Device complexity
If header and data are transmitted over the same channel, then interface simplicity is maintained, but receiver decoding complexity and latency increase
Solution Approach 1:
The transmission channel is segmented into separate logical channels for headers and data, both carried over the same physical lanes. The receiver separates these channels through protocol parsing, allowing independent processing of header and data portions. This logical segmentation reduces decoding complexity by handling control and payload information separately.
Solution Approach 2:
Headers are transmitted and processed before their associated data payloads. The receiver decodes headers in advance, determines data length and destination, and prepares reception buffers before the actual data arrives. This preliminary header processing reduces the critical path latency for data handling.
4Productivity
If interface bandwidth is increased to support higher data rates, then data transfer capability is improved, but pin count and manufacturing complexity increase
Solution Approach 1:
Multiple logical communication channels are merged onto a single physical lane structure. The interface uses time-division and code-division multiplexing to carry multiple data streams simultaneously over the same physical pins. This merging allows high aggregate bandwidth to be achieved without proportionally increasing the physical pin count.
Solution Approach 2:
The physical lane structure is designed to be universal and configurable, supporting multiple protocol types and data rates through software configuration rather than hardware changes. The same physical interface can be programmed to operate at different bandwidths and protocols, reducing the need for multiple specialized pin configurations.
Data Source
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AI summary
An interface (205) for coupling an agent to a fabric supports a load/store interconnect protocol and includes a header channel (515, 505) implemented on a first subset of a plurality of physical lanes, the first subset of lanes including first lanes to carry a header (505) of a packet based on the interconnect protocol and second lanes to carry metadata for the header (515). The interface additionally includes a data channel (510, 525) implemented on a separate second subset of the plurality of physical lanes, the second subset of lanes including third lanes to carry a payload of the packet (510) and fourth lanes to carry metadata for the payload (525).