Digital Computer Details TRIZ Cases

This case adds CDN capacity when local streaming demand crosses a threshold, balancing live delivery latency and bandwidth.

This case uses region-specific dielectric layers to balance current delivery and overshoot control across semiconductor memory cells.

This case routes packets around virtual channel buffers when credits and buffer status permit, reducing latency while preserving fairness.

Logged topology data predicts future network states, computes signatures, and recommends proactive remediation plans.

An orchestrator assigns weighted RDMA queue pairs and predicts bandwidth usage to balance traffic and resource utilization.

After self-refresh, control logic transfers memory data to non-volatile storage and powers off when no read command arrives.

This case uses text messaging to identify users, print mobile photos, and deliver them without app downloads or email exchanges.

A software-defined platform uses a metaverse key and network slicing to transform devices for seamless VR and AR experiences.

Exception notifications let chiplet processors handle atomic-operation traps without flag polling.

The guidance facility scores switch stack configurations and recommends connections for improved resiliency.

Path tracing packets record WL-PT-ID data through NFV chains, helping controllers verify VNF sequence and processing time.

A controller tests broadcast-address acknowledgement to select I2C or I3C, preventing protocol incompatibility on the management bus.

When direct telemetry fails, peer network devices forward diagnostics to the WAN assurance system for troubleshooting and remediation.

Gateway nodes translate virtual-router path lengths into route preferences for efficient, redundant cloud access.

This case partitions a GPU into configurable chiplets that operate as one or multiple GPUs, easing die size and manufacturing constraints.

A device protection agent detects network changes and uses a VPN to extend host security policies across disparate networks.

Proxy translation connects PLC data with microservices without manual serialization.

Graphical virtual routers simplify cloud-native SDN configuration and scaling.

Separate timeouts, selective heartbeats, and negative acknowledgments distinguish link failure, node downtime, and congestion.

When OTA updates disrupt processor links, last-active partition rollback reboots the AR wearable into a consistent state.

This HPC case uses selective heartbeats, negative acknowledgments, and timed retransmission to improve packet exchange reliability.

A tiered cache checks inference-card and local memory before the shared pool, reducing parameter lookup delay for neural network tasks.

This case scales multi-tenant RoCE across Layer-3 fabrics while preserving VLAN isolation, QoS, and congestion management.

A reconfigurable interconnect fabric switches between torus and twisted torus layouts to improve bandwidth and load balance.

This case uses lower-precision weights and higher-precision activations to reduce power while preserving inference accuracy.

This case shows how age-aware request ordering and returned-data availability reduce cache-miss stalls without extra buffers.

In-network telemetry lets receivers set sender rates and dynamically adjust control, reducing feedback overhead and improving flow fairness.

This case uses decoded path indexes for table-free forwarding, reducing frame headers, calculation overhead, and control-plane load.

The case vectorizes cloud resource activity, models event probabilities, and scores sequences to reduce anomaly-detection latency.

A broker and event-hub architecture reuses terminal data across services while RDMA enables fast, low-delay transfer with less CPU load.

Learn how VLAN-mapped ELPS groups isolate ring faults, reduce flooding, and support rapid protection switching.

A message-based processor system replaces large routing tables with compact control data to scale neural network cluster messaging.

Tag lines and service bits enable data sharing without host synchronization.

This case uses SmartNIC address management and RDMA processing to reduce CPU overhead at remote memory nodes.

Separate header and payload channels reduce decoding complexity and communication latency.