Virtual Channel Buffer Bypass for Fair, Low-Latency Routing
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Solution Overview
Problem
Existing interconnects face issues of head-of-line blocking and high latency due to packet buffering, leading to increased power consumption and inefficient data transmission.
Innovation Solution
Implementing a bypass path in interconnect nodes that allows data packets to bypass the virtual channel buffer when certain conditions are met, such as zero credits or empty partitions, reducing the need for writing and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packets are buffered at a node in the interconnect, then head of line blocking is reduced through virtual channel arbitration, but latency increases due to multiple clock cycles required for write and read operations
Solution Approach 1:
The patent extracts the buffering function selectively by providing a bypass path that allows packets to skip the buffer when conditions permit. The arbitration logic determines whether to route packets through the buffer or bypass it, thereby taking out the buffering delay when unnecessary while preserving buffering when needed for fairness.
Solution Approach 2:
The patent makes the data path dynamic by conditionally routing packets either through the buffer or via the bypass path based on real-time buffer status and credit availability. This dynamic switching allows the system to adapt between buffered and direct transmission modes to optimize both fairness and latency.
2Reliability
If packets are buffered at a node in the interconnect, then head of line blocking is reduced through virtual channel arbitration, but power consumption increases due to write and read operations
Solution Approach 1:
The patent removes the power-consuming buffer write and read operations by providing a bypass path. When packets can be forwarded immediately (buffer empty or credits available), they take the bypass route, eliminating unnecessary energy expenditure while preserving the ability to buffer when required for fairness.
Solution Approach 2:
The patent dynamically switches between buffered and direct transmission modes based on buffer status and credit availability. This dynamic operation allows the system to minimize power consumption by avoiding buffer operations when they are not strictly necessary for maintaining fairness among virtual channels.
3Loss of time
If a bypass path is provided for direct packet transmission, then latency and power consumption are reduced, but head of line blocking may occur if not properly controlled
Solution Approach 1:
The patent uses credit-based flow control as a feedback mechanism to regulate bypass path usage. Credits indicate buffer availability at the destination, and the arbitration logic uses this feedback to determine whether safe bypass transmission is possible, preventing head of line blocking by ensuring downstream readiness.
Solution Approach 2:
The patent performs preliminary checks of buffer status and credit availability before enabling bypass transmission. This preliminary action ensures that packets only take the bypass path when it is safe to do so, preventing head of line blocking while maintaining low latency benefits.
4Loss of time
If bypass path is enabled without conditions, then latency is minimized, but fairness between virtual channels deteriorates
Solution Approach 1:
The patent makes the bypass path dynamically controllable through arbitration logic that considers virtual channel fairness requirements. The system adaptively switches between buffered and direct transmission based on real-time conditions, ensuring low latency when possible while maintaining fairness when required.
Solution Approach 2:
The patent uses feedback from buffer status and credit availability to control bypass path access per virtual channel. This feedback mechanism ensures that bypass transmission does not compromise fairness, as the arbitration logic adjusts bypass eligibility based on current system state and fairness requirements.
Data Source
AI summary
A bypass path is provided in the node for reducing the latency and power consumption associated with writing to and reading from the VC buffer, and is enabled when certain conditions are met. Bypass is enabled for a received packet when there is no other data that is ready to be sent from the VC buffer, which is the case when all VCs either have zero credits or an empty partition in the buffer. In this way, data arriving at the node is prevented from using the bypass path to take priority over data already held in the VC buffer and ready for transmission.