Twisted Torus Processor Networks for Non-Cubical Load Balance
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Solution Overview
Problem
Existing processor topologies struggle to provide optimal performance for varying computational tasks due to asymmetrical network configurations, leading to inefficiencies in communication bandwidth and load balance.
Innovation Solution
Implementing a reconfigurable interconnect fabric that allows for both torus and twisted torus interconnection schemes, enabling dynamic allocation of processing nodes into symmetric network topologies tailored to specific task requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a standard torus interconnection scheme is used for non-cubical node configurations, then the network topology is simpler to implement, but the network performance deteriorates due to asymmetry leading to lower bisection bandwidth, worse load balance, and higher network diameter
Solution Approach 1:
The patent applies asymmetry by introducing a twist offset to the wraparound connections in the torus interconnection scheme. Specifically, when connecting processing nodes in non-cubical configurations (where dimensions are not equal), the wraparound connection in one dimension is offset by a calculated amount based on the dimension ratios. This deliberate asymmetric modification to the otherwise symmetric torus structure creates the twisted torus configuration that balances the network and improves performance metrics while maintaining implementability.
2Adaptability or versatility
If processing nodes are allocated in non-cubical configurations to match specific task requirements, then the adaptability to different computational tasks is improved, but the network performance worsens due to asymmetrical topology
Solution Approach 1:
The patent changes the interconnection parameters by introducing a twist offset that is calculated based on the specific dimensional parameters of the non-cubical configuration. The offset amount is determined by the ratio of dimensions (e.g., for an 8x4x4 configuration, the offset in the 8-node dimension would be 4). This parameter change transforms the standard torus interconnection into a twisted torus that is specifically adapted to the non-cubical node arrangement, thereby maintaining both the adaptability to different task configurations and the communication efficiency through balanced network topology.
3Adaptability or versatility
If a reconfigurable interconnect fabric is implemented to support multiple topologies, then the versatility of the system is improved, but the device complexity increases due to additional switching elements and configuration management
Solution Approach 1:
The patent implements a reconfigurable interconnect fabric that serves multiple functions: it can configure standard torus topologies for cubical node arrangements and twisted torus topologies for non-cubical arrangements. The same physical interconnect infrastructure with switching elements handles both configuration types, eliminating the need for separate dedicated interconnect structures. This multi-functionality achieves versatility across different task requirements while managing complexity through a unified reconfigurable platform rather than multiple specialized systems.
Data Source
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AI summary
Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.