Volatile Memory Self-Refresh Control for Low-Power Data Retention

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Solution Overview

Problem

The high power consumption due to self-refresh operations in volatile memory devices, such as DRAM, in electronic control units (ECUs) of vehicles when powered off, necessitates a solution to reduce operation power and maintain data integrity.

Innovation Solution

A volatile memory device with control logic that performs a self-refresh operation, requests data transfer to a non-volatile memory upon a threshold time elapsed, monitors for read commands, and powers off if none are received, and a System on Chip (SoC) that manages these operations to minimize power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If volatile memory performs self-refresh operation to maintain data when ECU is powered off, then data integrity is preserved, but current consumption increases

Engineering Contradiction:
Improvedata integrityVSAvoidcurrent consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system performs preliminary actions by transferring data from volatile memory to non-volatile memory before the ECU is fully powered off. The control logic monitors the power-off state and initiates data transfer in advance, allowing the volatile memory to be powered off without compromising data integrity. This preliminary data transfer eliminates the need for continuous self-refresh operations during the power-off state, thereby reducing current consumption while maintaining data safety.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If volatile memory continues self-refresh operation after first threshold time elapsed, then data is maintained, but unnecessary power consumption occurs

Engineering Contradiction:
Improvedata maintenanceVSAvoidunnecessary power consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The control logic implements feedback mechanisms by monitoring the power state and timing information to determine when self-refresh operations are necessary. After the first threshold time elapsed since power-off, the system receives feedback about the power state and adjusts its behavior accordingly - stopping unnecessary self-refresh operations and initiating data transfer to non-volatile memory. This feedback-driven approach ensures data is maintained only when necessary, eliminating unnecessary power consumption.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts its operation mode based on real-time conditions. The control logic monitors the elapsed time since power-off and transitions between different operational states: maintaining self-refresh during the critical initial period, then switching to data transfer mode after the first threshold time. This dynamic adaptation allows the system to optimize between data maintenance and power consumption based on the actual power state and timing conditions.

Inventive Principle:
Principle #15Dynamics

3Reliability

If control logic monitors read commands continuously, then data transfer is ensured, but operation complexity increases

Engineering Contradiction:
Improvedata transfer assuranceVSAvoidcontrol logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of continuous monitoring, the control logic employs periodic action by monitoring read commands at specific intervals or after specific events (such as after the first threshold time elapsed). The system checks for read commands periodically during the data transfer phase, which ensures data transfer reliability while significantly reducing the operational complexity compared to continuous monitoring. This periodic approach maintains the necessary reliability threshold while simplifying the control logic.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP4586255A1Volatile memory, system on chip and electronic device comprising the same
Publication Date: 2025.07.16 SAMSUNG ELECTRONICS CO LTD
  • EP4586255A1 patent drawingFigure 1
  • EP4586255A1 patent drawingFigure 2
  • EP4586255A1 patent drawingFigure 3

AI summary

A volatile memory device comprises a memory cell array including a plurality of memory cells storing data, and control logic controlling read and write operations for the plurality of memory cells. The control logic is configured to receive a command instructing a self-refresh operation from an external host device, to perform the self-refresh operation in response to the received command, to request the external host device to transfer data stored in the plurality of memory cells in response to a performance time of the self-refresh operation having elapsed a first threshold time, to monitor a read command received from the external host device in response to receiving a notification of self-refresh operation termination and a read command from the external host device, and to enter a power off state in response to the read command not being received for a second threshold time.