Stress Patterned Thin Substrates for Wafer Warpage Correction
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Solution Overview
Problem
Warping of silicon wafers (wafer warpage) in semiconductor manufacturing, particularly in 3D NAND flash memory and group III-V semiconductor devices, leads to misalignment issues and increased manufacturing costs due to stress-induced distortions from epitaxy and coating processes, which existing correction technologies cannot fully address.
Innovation Solution
The development of general stress patterning techniques that create equibiaxial and uniaxial stress fields using micro-lithographic processes and reactive ion etching to induce free-form deformations in thin substrates, allowing for precise control of stress orientation and magnitude, enabling the correction of complex distortions such as astigmatism and trefoil deformations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D stacking and bonding technology is used to increase storage capacity, then bit number per unit area is increased, but stress in layers increases causing wafer warpage and misalignment
Solution Approach 1:
The patent applies preliminary anti-action by introducing stress counter layers with opposite stress characteristics before the bonding process. These counter layers are designed to generate stresses that oppose the inherent stresses in the stacked structure, thereby preventing wafer warpage and misalignment from occurring in the first place during the 3D stacking process
Solution Approach 2:
The patent employs parameter changes by systematically varying the thickness, material composition, and stress characteristics of the stress counter layers. By adjusting these parameters, the patent optimizes the counter-stress effect to precisely compensate for the stress-induced warpage while maintaining manufacturing precision in 3D stacked structures
2Ease of manufacture
If traditional grinding and polishing methods are used for ultra-precision machining, then material can be removed, but residual stress relaxation causes failure to produce designed topology
Solution Approach 1:
The patent replaces the traditional mechanical grinding and polishing system with a stress-based deformation system. Instead of mechanically removing material to achieve the desired topology, the patent uses controlled stress fields to induce elastic deformation that shapes the substrate, thereby avoiding stress relaxation issues inherent in mechanical material removal
Solution Approach 2:
The patent utilizes parameter changes by controlling the magnitude, direction, and distribution of applied stresses to precisely induce the desired deformation patterns. By adjusting stress parameters, the patent can transform the substrate into complex topologies such as aspheric surfaces while maintaining manufacturing precision without relying on traditional mechanical machining
3Measurement precision
If post-correction technologies like thermal oxide patterning are used, then coating-induced distortion can be corrected with precision of approximately 0.5 arc-second, but mid-and-low frequency errors from polishing and grinding cannot be eliminated
Solution Approach 1:
The patent applies preliminary action by implementing stress-based figure correction during the manufacturing process itself, before final assembly and testing. By correcting both high-frequency coating-induced errors and low-frequency machining errors in advance through controlled stress deformation, the patent eliminates the need for subsequent post-correction technologies and ensures complete figure accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These techniques effectively control deformations in semiconductor devices and thin substrates, improving manufacturing precision and reducing costs by enabling precise reshaping of substrates and correcting stress-induced distortions that previous methods could not fully address.
Implementation Method 1
These methods can also produce an arbitrary in-plane stress orientation, called a general stress field, that can be used to induce free-form deformations in thin substrates
Implementation Method 2
A known way to mitigate coating-stress induced distortion in thin X-ray telescope silicon mirrors with high precision and low cost can be through a surface-stress-based figure correction technique that includes a thermal oxide patterning method
Data Source
AI summary
A device includes a substrate and a stressed layer disposed on a first surface of the substrate. The stressed layer includes: a first set of patterns having a predetermined geometry, size, and arrangement selected to control an equibiaxial stress field of the stressed layer, wherein the equibiaxial stress field varies in magnitude over the first surface of the substrate, and a second set of patterns etched into the first set of patterns and the substrate, the second set of patterns comprising a plurality of substantially parallel lines arranged to control at least a uniaxial stress field of the stressed layer, wherein the uniaxial stress field varies in magnitude over the first surface of the substrate.