Stressed Dielectric Layer for Transistor Strain Transfer
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Solution Overview
Problem
Conventional techniques for forming stressed dielectric layers in highly scaled transistor elements suffer from reduced efficiency and non-uniformities during patterning and contact opening formation, leading to defects and reduced transistor performance.
Innovation Solution
A technique involving the formation of a highly stressed dielectric material above transistors, followed by stress relaxation, allowing for the deposition of a further stress-inducing layer on a substantially relaxed material, which enhances transistor performance by reducing voids and irregularities, and enabling efficient stress transfer without the need for complex material removal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a highly stressed dielectric layer is formed directly above transistors to induce strain for performance enhancement, then transistor drive current capability is improved, but voids and irregularities occur during deposition and patterning processes
Solution Approach 1:
A stress-neutral dielectric layer is introduced as an intermediary between the substrate and the highly stressed dielectric layer. This intermediate layer mediates the stress transfer process, allowing the highly stressed layer to be deposited uniformly without direct contact with the transistor channels, thereby preventing void formation while still enabling strain induction in the channel regions.
Solution Approach 2:
The stress-neutral dielectric layer is formed preliminarily before depositing the highly stressed dielectric layer. This preliminary action prepares a uniform, stress-free foundation that enables subsequent deposition of the stressed layer without the harmful effects that would occur if the stressed layer were deposited directly on the transistor structures.
2Adaptability or versatility
If conventional dual stress line approaches are used to apply different stresses to N-channel and P-channel transistors, then selective stress enhancement is achieved, but complex material removal processes are required
Solution Approach 1:
The dielectric stack is segmented into functionally distinct layers: a stress-neutral dielectric layer for uniform support and a highly stressed dielectric layer for strain induction. This segmentation allows different regions to serve different purposes without requiring complex selective removal processes, as each layer can be formed continuously across both N-channel and P-channel transistor regions.
Solution Approach 2:
The highly stressed dielectric layer provides localized strain enhancement to channel regions beneath it, while the stress-neutral layer maintains uniform mechanical properties throughout the structure. This local quality differentiation enables selective stress application to different transistor types through the inherent stress characteristics of the dielectric materials rather than through complex processing steps.
3Speed
If the channel length is reduced to increase operating speed, then transistor switching speed is improved, but short channel effects increase and controllability of channel conductivity decreases
Solution Approach 1:
The physical state of the channel region is changed by inducing mechanical strain through the highly stressed dielectric layer. This parameter change in the crystal lattice structure of the semiconductor channel modifies carrier mobility and conductivity characteristics, enabling improved operating speed while maintaining controllability even at reduced channel lengths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the drive current capability of transistors, reduces leakage currents, and enhances transistor performance by maintaining a stress-neutral layer above one type of transistor while applying compressive or tensile stress to another, thus overcoming limitations in conventional dual stress line approaches.
Implementation Method 1
Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device
Implementation Method 2
creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons
Implementation Method 3
followed by stress relaxation, allowing for the deposition of a further stress-inducing layer on a substantially relaxed material
Data Source
AI summary
By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.