Stressed Dielectric Layer Strain Engineering in Transistors
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Solution Overview
Problem
The challenge in enhancing transistor performance in integrated circuits lies in efficiently increasing strain in the channel region while avoiding complex manufacturing processes and minimizing the impact on device topography, particularly due to limitations in depositing stressed silicon nitride material, which can lead to reduced strain transfer and process nonuniformities.
Innovation Solution
The technique involves modifying the transistor topography during manufacturing to allow for increased deposition of highly stressed dielectric material by using placeholder structures, enabling the deposition of additional stressed dielectric layers without compromising gap-filling capabilities or increasing fringing capacitance, thereby enhancing strain in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the gate insulation layer is reduced to compensate for short channel effects, then the controllability of the channel is improved, but the charge carrier mobility in the channel region is reduced
Solution Approach 1:
The patent changes the physical state of the channel region by introducing mechanical strain through stressed dielectric layers. This parameter change (strain state) directly affects charge carrier mobility, allowing improved mobility without reducing gate insulation thickness, thus resolving the contradiction between channel controllability and charge carrier mobility
2Speed
If the channel length is reduced to increase operating speed, then the operating speed of the integrated circuits is improved, but short channel effects become more significant and channel controllability deteriorates
Solution Approach 1:
The patent introduces strain as a new parameter to control channel properties. By applying mechanical strain through stressed dielectric layers, the patent can maintain good channel controllability even with reduced channel length, thereby achieving high operating speed without sacrificing reliability
3Manufacturing precision
If a high amount of stressed silicon nitride material is deposited to increase strain in the channel region, then the charge carrier mobility is improved, but the deposition process creates voids and nonuniformities
Solution Approach 1:
The patent divides the single thick stressed dielectric layer into multiple thinner layers. This segmentation allows each layer to be deposited uniformly without creating voids, while the cumulative strain from multiple layers still achieves the desired charge carrier mobility improvement
Solution Approach 2:
The patent introduces vertical spacing between stressed dielectric layers through placeholder structures. This dimensional approach allows stress to be applied effectively while maintaining deposition uniformity, as each layer can be deposited independently without the defects associated with thick single-layer deposition
4Manufacturing precision
If placeholder structures are used to increase device height for better strain transfer, then the strain in the channel region is improved, but the device topography becomes more complex
Solution Approach 1:
The patent extracts the placeholder structures from the active device region and places them in isolation. This allows the placeholder structures to serve their function of enabling thick stressed dielectric deposition without adding complexity to the transistor structure itself, as they can be selectively removed or isolated from the active device topography
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases strain in the channel region, improving transistor performance without requiring complex processes or additional strain-inducing mechanisms, while maintaining reliable fill behavior and avoiding voids in the dielectric material, thus enhancing the efficiency of the strain-inducing mechanism.
Implementation Method 1
transistor performance is increased by producing strain in the channel region on the basis of a dielectric layer comprising a high intrinsic stress
Data Source
AI summary
By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.