String Select Transistor Threshold Layout for Uniform NAND Erase
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Solution Overview
Problem
Non-volatile memory devices with multi-hole structures experience performance differences due to intrinsic characteristic variations among channel holes, leading to uneven erase speeds and gate induced drain leakage (GIDL) currents.
Innovation Solution
Incorporating string select transistors with different threshold voltages in memory devices, where outer transistors have higher threshold voltages than inner transistors, to compensate for uneven erase speeds and minimize GIDL currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If string select transistors with different threshold voltages are used to compensate for performance differences, then erase speed uniformity is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by assigning different threshold voltages to string select transistors based on their specific positions within the memory block. Outer string select transistors (closer to bit lines) are given higher threshold voltages, while inner string select transistors (farther from bit lines) are given lower threshold voltages. This localized differentiation compensates for the varying electrical characteristics caused by different distances from the bit lines, ensuring uniform erase speeds across all cell strings despite the increased device complexity.
2Object-generated harmful factors
If higher threshold voltage transistors are used for outer string select lines, then GIDL current is reduced, but erase operation efficiency may be compromised
Solution Approach 1:
The patent employs parameter changes by systematically varying the threshold voltage parameter of string select transistors according to their spatial location. Outer string select transistors are designed with higher threshold voltages to suppress GIDL currents generated during erase operations, while inner string select transistors use lower threshold voltages to maintain adequate erase efficiency. This parameter optimization balances the trade-off between reducing harmful GIDL currents and preserving erase operation efficiency across different regions of the memory block.
3Quantity of substance
If multi-hole structure is increased for higher capacity, then storage density is improved, but performance variation among channel holes increases
Solution Approach 1:
The patent addresses performance variation in multi-hole structures by applying local quality differentiation through position-dependent threshold voltage assignment. As the number of channel holes (cell strings) increases to achieve higher storage capacity, the varying distances from bit lines create performance inconsistencies. By assigning higher threshold voltages to outer string select transistors and lower threshold voltages to inner string select transistors, the patent compensates for these inherent variations, ensuring that all cell strings maintain consistent erase performance despite the increased quantity and spatial distribution of storage elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform erase speeds across channel holes by adjusting threshold voltages, reducing GIDL currents, and enhancing the overall erase operation efficiency.
Implementation Method 1
a first threshold voltage of a first transistor connected to the first string select line is higher than a second threshold voltage of a second transistor connected to the second string select line
Data Source
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AI summary
A memory device including: a memory cell array including a plurality of memory blocks; a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block of the plurality of memory blocks on which an erase operation is to be performed; and a control logic circuit configured to control the memory cell array and the voltage generator, wherein, during the erase operation, after a precharge voltage is applied to a plurality of string select lines connected to the target block, the control logic circuit is further configured to provide the erase voltage to a plurality of bit lines connected to the plurality of string select lines, wherein the plurality of string select lines includes a first string select line and a second string select line, wherein a first distance between the first string select line and ends of a plurality of word lines connected to the target block is less than a second distance between the second string select line and the ends of the plurality of word lines, and wherein a first threshold voltage of a first transistor connected to the first string select line is higher than a second threshold voltage of a second transistor connected to the second string select line.