Strobe Signal Control Circuit for Memory Write Timing
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Solution Overview
Problem
Conventional strobe signal controlling circuits in semiconductor memory devices fail to properly synchronize the write pulse signal with the clock signal, leading to incorrect generation of DQS signals, resulting in write failures when the write pulse signal is generated prior to the clock signal.
Innovation Solution
The proposed strobe signal controlling circuit includes an initial write controller that synchronizes the write pulse signal with the clock signal, a control signal generator that produces a control signal to manage the DQS signal output, and a reset signal generator that ensures the DQS signal outputting unit is reset in synchronization with the control signal, preventing premature signal shifts and maintaining correct signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the write pulse signal is generated prior to the clock signal, then the initial write controller can generate the WT0 signal early, but the reset signal generator resets the DQS signal outputting unit before the clock signal is ready, causing signal synchronization failure
Solution Approach 1:
The patent applies preliminary action by generating the WT0 signal early in response to the write pulse signal WTP, before the clock signal CLK is ready. The initial write controller outputs WT0 immediately when WTP is detected, allowing the signal generation to start early without waiting for the clock signal. This preliminary action is compensated by the reset signal generator which ensures proper timing alignment later.
Solution Approach 2:
The patent uses feedback through the reset signal generator that monitors both the write pulse signal WTP and the clock signal CLK. When WTP is detected, the reset signal generator generates a reset signal RSTB after the clock signal becomes ready, feeding back to the DQS signal outputting unit to ensure it is in the correct state. This feedback mechanism adjusts the timing based on the actual clock signal status, resolving the synchronization issue caused by early WT0 generation.
2Productivity
If the reset signal is generated immediately upon receiving the write pulse signal, then the DQS signal outputting unit is reset early, but this causes the WT0 signal to be shifted incorrectly when the clock signal is not yet ready
Solution Approach 1:
The initial write controller performs preliminary action by generating WT0 early in response to WTP, preparing the signal sequence in advance. This allows the write operation to proceed without delay even though the clock signal may not be ready immediately.
Solution Approach 2:
The patent applies dynamics by making the reset signal generation conditional and adaptive. The reset signal generator dynamically adjusts the timing of RSTB based on the actual readiness of the clock signal CLK. When CLK is ready, RSTB is generated to reset the DQS signal outputting unit at the appropriate moment. This dynamic timing adjustment ensures that even though WT0 was generated early, the subsequent signals are properly synchronized when the clock becomes available, maintaining both productivity and timing precision.
3Ease of operation
If the DQS signal outputting unit is reset before the clock signal is ready, then the unit is prepared early for signal output, but the shifted WT0 signal causes incorrect DQS signal generation
Solution Approach 1:
The reset signal generator implements feedback by monitoring both the write pulse signal WTP and the clock signal CLK status. It generates the reset signal RSTB only when both conditions are met: WTP has been detected (indicating a write operation is needed) and CLK is ready (ensuring proper timing). This feedback mechanism ensures the DQS signal outputting unit is reset at the optimal moment, maintaining both ease of operation and signal correctness.
Solution Approach 2:
The system dynamically adjusts the reset timing based on the actual clock signal status. Rather than using a fixed reset timing, the reset signal generator adapts RSTB generation to the actual readiness of CLK. This dynamic approach allows the system to prepare the DQS signal outputting unit early when possible, while ensuring the reset occurs at the correct moment to maintain signal correctness, resolving the contradiction between ease of operation and reliability.
Data Source
AI summary
A strobe signal controlling circuit is provided which includes an initial write controller configured to outputs a write pulse signal, which is activated in a write command, in synchronization with a clock signal, a DQS signal outputting unit configured to outputs a write DQS signal by synchronizing an output signal of the initial write controller to the clock signal, a control signal generator configured to generates a control signal in response to the output signal of the initial write controller, and a reset signal generator configured to responds to a reset signal and a DQS enable signal to output a reset signal to the DQS signal outputting module in synchronization with the control signal.