Structured Carrier Solder Wetting for LED Luminance Uniformity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing methods for manufacturing lighting means with optoelectronic components often result in uneven light distribution and luminance due to imprecise placement, which can be exacerbated by heat dissipation issues.

Innovation Solution

A method involving a carrier with a planar chip mounting area structured into solder-repellent and solder-attracting subareas, where optoelectronic components are fixed using solder that primarily wets the attracting subareas, allowing for improved heat dissipation and uniform light emission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If optoelectronic components are placed on a common chip to achieve high luminance levels, then light output is improved, but placement precision becomes difficult to control resulting in uneven light distribution

Engineering Contradiction:
Improvelight outputVSAvoidplacement precision
Core Design Contradiction:
Illumination intensityVSManufacturing precision

Solution Approach 1:

The chip mounting area is segmented into first subareas (solder-repellent) and second subareas (solder-attracting) using structuring. This segmentation creates distinct zones that guide solder placement automatically, ensuring optoelectronic components are positioned precisely in the intended locations without requiring manual precision placement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The solder acts as an intermediary that responds to the structured surface properties. By creating solder-repellent and solder-attracting areas, the system uses the solder's wetting behavior as a mediator to automatically position components correctly during the soldering process, eliminating the need for high-precision manual placement.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Illumination intensity

If multiple optoelectronic components are placed close together on a common chip, then luminance uniformity is improved, but heat dissipation becomes more difficult

Engineering Contradiction:
Improveluminance uniformityVSAvoidheat dissipation
Core Design Contradiction:
Illumination intensityVSTemperature

Solution Approach 1:

The chip mounting area exhibits local quality variations through structuring, with different subareas having distinct solder-repellent or solder-attracting properties. This local differentiation enables precise component positioning while maintaining optimal spacing for heat dissipation, even when components are placed close together to achieve uniform luminance.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances luminance uniformity and heat dissipation, enabling precise placement and reduced failure probability of optoelectronic components, resulting in improved light source performance.

Implementation Method 1

a solder is applied to the planar chip mounting area so that it wets the at least one second partial area

Methodology Applied
Scientific EffectWetting: Wetting

Implementation Method 2

the first partial area being solder-repellent after structuring

Methodology Applied
Scientific EffectSolder-repellent property: Hydrophobe

Implementation Method 3

a carrier serving as a heat sink is provided

Methodology Applied
Scientific EffectHeat dissipation: Conduction (thermal)

Data Source

PatentEP2371000B1Method for producing lamps
Publication Date: 2016.10.26 OSRAM OPTO SEMICON GMBH & CO OHG
  • EP2371000B1 patent drawingFigure 1~2
  • EP2371000B1 patent drawingFigure 3~4B
  • EP2371000B1 patent drawingFigure 4C~4E

AI summary

A method for producing lamps proposes the provision of a carrier serving as a heat sink, comprising a planar chip assembly region. The planar chip assembly region is structured so as to create a first partial region and at least one second partial region. To this end, the first partial region has a solder-repelling property after structuring. Thereafter, a solder is applied onto the planar chip assembly region, so that it moistens the at least one second partial region. At least one optoelectronic body is attached in the at least one second partial region to the carrier by way of the solder. Finally, contacts are formed on the optoelectronic luminous element for supplying electric energy.