STT-MTJ In-Memory Logic Circuit for Reconfigurable Edge Extraction
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Solution Overview
Problem
Conventional image edge extraction circuits face limitations due to the 'memory wall' and 'power limit throttling' issues, being restricted to specific functions and requiring separate memory and processor architectures, which hinders their ability to perform reconfigurable logic operations efficiently.
Innovation Solution
The development of an in-memory computing unit and circuit with reconfigurable logic using STT-MTJs, where multiple STT-MTJs are connected in a double-input single-output configuration, allowing for the implementation of NAND, NOR, AND, and OR logical operations by adjusting voltage and dimension ratios, and utilizing switches to reconfigure between different logic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional separate memory and processor architecture is used, then device complexity is reduced, but productivity deteriorates due to memory wall and power limit throttling
Solution Approach 1:
The patent merges memory and processing functions into a single in-memory computing unit. The STT-MTJ device simultaneously performs data storage and logical operations, eliminating the need for separate memory and processor components. This integration directly addresses the memory wall problem by allowing computation to occur where data is stored, improving productivity without significantly increasing device complexity.
Solution Approach 2:
The STT-MTJ device is designed to perform multiple functions: it serves as both a memory element and a logic gate. By configuring the same hardware structure with different voltage inputs and initialization states, the device can implement various logical operations (NAND, NOR, AND, OR), thereby improving computing productivity while maintaining relatively simple device architecture.
2Adaptability or versatility
If conventional specific function circuits are used, then device complexity is reduced, but adaptability deteriorates due to limitation to specific functions
Solution Approach 1:
The in-memory computing unit employs dynamic reconfiguration capabilities where the same hardware structure can be programmed to perform different logical operations. By changing voltage inputs, initialization states, and connection configurations, the device adapts between NAND, NOR, AND, and OR operations, significantly improving adaptability while keeping the physical device structure relatively simple.
Solution Approach 2:
The patent utilizes parameter changes in voltage magnitude and polarity to switch between different logical operations. The STT-MTJ device responds to different voltage thresholds and timing sequences to perform various logic functions, enabling high adaptability through electrical parameter modulation rather than physical reconfiguration, thus maintaining low device complexity.
3Loss of time
If multiple memory access operations are performed, then manufacturing precision is reduced, but loss of time deteriorates due to additional access cycles
Solution Approach 1:
The patent combines memory storage and logic processing into a single integrated unit, eliminating the need for separate read and write access cycles to different components. The in-memory computing unit performs logical operations directly on stored data without requiring data to be transferred out and back into memory, significantly reducing access time while the integration is achieved through standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient in-memory computing by allowing data storage and logical operations within the same circuit architecture, eliminating the need for additional memory access and reducing power consumption, while enabling flexible implementation of various image edge extraction operators.
Implementation Method 1
two input STT-MTJs and one output STT-MTJ... Free layer sides of the two input STT-MTJs serves as a voltage input terminal
Data Source
AI summary
An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.