STT-MTJ NVSRAM Cell Structure for Fast Access and Data Retention
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Solution Overview
Problem
Existing static random access memory (SRAM) loses its content when powered down, making it volatile, while non-volatile memory solutions either lack speed or are costly.
Innovation Solution
A non-volatile static random-access memory (NVSRAM) device integrates a static random access memory (SRAM) unit with a spin-transfer torque magneto-resistive random-access memory (STT-MRAM) unit, allowing for fast access and unlimited endurance with data retention using magnetic tunnel junction (MTJ) structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM is used for fast access, then speed is improved, but data is lost when powered down (volatility)
Solution Approach 1:
The memory cell is divided into two independent units: an SRAM unit for fast access operations and an STT-MRAM unit for non-volatile data storage. Each unit operates independently but shares the same cell structure, allowing the system to leverage the speed of SRAM while maintaining the data retention capabilities of MRAM.
Solution Approach 2:
The patent merges SRAM and STT-MRAM units into a single hybrid memory cell structure. The SRAM unit provides fast read/write operations while the STT-MRAM unit provides non-volatile storage. The two units are integrated at the cell level and work together to achieve both high speed and data retention.
2Reliability
If non-volatile memory is used for data retention, then reliability is improved, but access speed is reduced
Solution Approach 1:
The memory cell is divided into two independent units: an SRAM unit for fast access operations and an STT-MRAM unit for non-volatile data storage. Each unit operates independently but shares the same cell structure, allowing the system to leverage the speed of SRAM while maintaining the data retention capabilities of MRAM.
Solution Approach 2:
The patent merges SRAM and STT-MRAM units into a single hybrid memory cell structure. The SRAM unit provides fast read/write operations while the STT-MRAM unit provides non-volatile storage. The two units are integrated at the cell level and work together to achieve both high speed and data retention.
3Speed
If hybrid SRAM-MRAM structure is used, then both speed and data retention are improved, but device complexity increases
Solution Approach 1:
The hybrid memory cell structure serves multiple functions: the SRAM unit handles fast read/write operations while the STT-MRAM unit provides non-volatile storage. The shared cell structure and bit line connections enable both units to participate in read operations, making the system multi-functional without requiring completely separate structures.
Solution Approach 2:
The system dynamically switches between different operational modes: during normal operation, the SRAM unit is actively used for fast access; during power loss events, the STT-MRAM unit takes over for data retention; and during restore operations, data is transferred between units. This dynamic behavior allows the system to adapt to different operational requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The NVSRAM device provides fast access with unlimited endurance and no read/write errors, retaining data in STT-MRAM units during power loss and automatically restoring data to SRAM units upon power restoration.
Implementation Method 1
the data in the corresponding STT-MRAM units are retained
Implementation Method 2
spin-transfer torque magneto-resistive random-access memory (STT-MRAM or MRAM) unit
Implementation Method 3
spin-transfer torque magneto-resistive random-access memory (STT-MRAM or MRAM) unit
Data Source
AI summary
A non-volatile static random-access memory (NVSRAM) device includes at least one array of NVSRAM cells. Each NVSRAM cell includes an SRAM unit and an MRAM unit. The SRAM unit includes at least six transistors, and the MRAM unit includes at least two-transistors and two magnetic tunnel junction (MTJ) structures. The SRAM units are accessed during normal read/write operations to allows for fast access to the NVSRAM cells with unlimited endurance and without read/write error rate issues. Hidden MRAM write operations in NVSRAM cells that are not accessed for normal read/write operations may be activated manually or automatically to back up the data stored in the corresponding SRAM units. When the NVSRAM device loses power, data stored in the SRAM units are lost, while the data backed-up in corresponding MRAM units are retained. When power is restored, an automatic data restore write cycle is started, during which the SRAM units recover their data from their corresponding MRAM units.


