Sub-block Erase Compensation in 3D NAND Memory
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Solution Overview
Problem
Conventional three-dimensional NAND memory systems face inefficiencies due to the need for uniform erase operations across large blocks, which can lead to uneven wear and potential premature failure of sub-blocks, as entire blocks are erased simultaneously, disregarding the state of individual sub-blocks.
Innovation Solution
Implementing a method to perform sub-block erase operations adaptively, where access parameters for memory cells in a NAND array are determined based on the condition of adjacent sub-blocks, allowing for differentiated voltage applications during read, write, and erase operations, and incorporating a determination circuit to manage sub-block states and parameter storage for optimized access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If entire blocks are erased simultaneously, then erase operation simplicity is maintained, but uneven wear and premature failure occur in sub-blocks
Solution Approach 1:
The erase block is divided into multiple sub-blocks that can be independently erased. The method identifies and erases only the specific sub-block containing target memory cells rather than erasing the entire block, enabling selective erase operations that reduce unnecessary wear on other sub-blocks while maintaining operational simplicity through automated sub-block identification and management.
2Reliability
If sub-block erase is implemented, then wear-leveling and reliability improve, but access operation complexity increases due to parameter adjustments
Solution Approach 1:
The system dynamically adjusts access parameters based on the erase state of sub-blocks. When accessing memory cells in a sub-block that has been erased while adjacent sub-blocks remain programmed, the system automatically modifies read and verify voltages to account for resistance changes in series-connected cells. This dynamic adaptation ensures reliable operation without requiring manual intervention, balancing improved reliability with automated complexity management.
Solution Approach 2:
The method incorporates feedback mechanisms where the system determines the erase state of sub-blocks before access operations and adjusts parameters accordingly. The system monitors the condition of memory cells and modifies access voltages based on this information, ensuring optimal performance for mixed-state block configurations while automatically managing the complexity of parameter adjustments.
3Manufacturing precision
If access parameters are dynamically adjusted, then programming accuracy improves, but operation time increases due to additional determination steps
Solution Approach 1:
The system performs preliminary determination of sub-block erase states before executing access operations. By identifying which sub-blocks have been erased in advance, the system can pre-calculate and apply appropriate access parameters, ensuring programming accuracy is maintained while minimizing time overhead through efficient state detection and parameter selection algorithms.
Data Source
AI summary
A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme.