Sub-Driver Signal Line Circuits for Digital Skew Reduction
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Solution Overview
Problem
As digital signal transmission speeds increase, skew between adjacent signal lines becomes problematic due to differences in physical length, capacitance, and output impedance, limiting circuit speed and operating margins, and existing solutions like DLL and PLL techniques add complexity and introduce delay.
Innovation Solution
The introduction of sub-driver circuits that source or sink current responsive to digital signal transitions, maintaining a high impedance state otherwise, to reduce skew between signal lines by compensating for parasitic capacitances and variable delays, without increasing circuit complexity or introducing lag.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DLL or PLL techniques are used to lock signals together, then skew between signal lines is reduced, but circuit complexity increases and additional delay is introduced due to locking time
Solution Approach 1:
The patent extracts the skew compensation function from complex DLL/PLL circuits and implements it through a simplified sub-driver circuit that directly senses signal transitions and provides compensating current, eliminating the need for locking mechanisms while maintaining skew reduction capability
Solution Approach 2:
The sub-driver circuit automatically detects signal transitions on adjacent lines and self-adjusts its current sourcing/sinking behavior to compensate for skew, without requiring external control signals or locking sequences, thereby reducing circuit complexity
2Reliability
If additional delay is added to the short delay path to equalize delays, then skew is reduced, but circuit complexity increases and implementation becomes difficult when time delay difference is variable
Solution Approach 1:
The patent implements a dynamic skew compensation mechanism where the sub-driver circuit continuously monitors signal transitions and adjusts its compensating current in real-time, allowing the system to adapt to variable time delay differences without requiring fixed delay equalization circuits
Solution Approach 2:
The sub-driver circuit changes its operational parameters (current sourcing/sinking amount and timing) based on detected signal transitions, enabling flexible compensation for variable skew conditions without requiring physical circuit modifications
3Reliability
If sub-driver circuits source or sink current responsive to signal transitions, then skew is reduced and parasitic capacitances are compensated, but additional current switching activity increases power consumption
Solution Approach 1:
The sub-driver circuit operates in a periodic manner, activating current sourcing or sinking only during detected signal transitions rather than continuously, thereby reducing average power consumption while maintaining effective skew compensation at critical moments
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces skew between signal lines, compensating for parasitic capacitances and variable delays, while maintaining simplicity and real-time operation without the need for phase lock loop or delay lock loop locking times.
Implementation Method 1
skew may be introduced among adjacent signal lines... the different signal lines may have different capacitances (actual and/or parasitic), which may also cause skew
Data Source
AI summary
Circuits, methods and systems are provided to reduce skew between a first digital signal that is transmitted by a first driver circuit over a first signal line, and a second digital signal that is transmitted by a second driver circuit over a second signal line. Skew may be reduced by sourcing or sinking additional current to or from the first signal line in response to the first digital signal and the second digital signal transitioning to opposite logical values, and otherwise refraining from sourcing or sinking the additional current to or from the first signal line. Skew may also be reduced between the first digital signal that is transmitted by the first driver circuit over the first signal line and a third digital signal that is transmitted by a third driver circuit over a third signal line by sourcing or sinking additional current to or from the first signal line in response to the first digital signal and the third digital signal transitioning to opposite logical values, and to otherwise refrain from sourcing or sinking the additional current to or from the first signal line.


