Sub-Fin Doping in FinFETs to Cut Leakage and Vt Variation
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Solution Overview
Problem
Conventional methods for fabricating multi-gate transistors, such as tri-gate transistors, face challenges in scaling down dimensions while maintaining device performance, as they result in high doping levels in fin regions, leading to increased ionized impurity scattering and random variation in threshold voltage, which degrades carrier mobility and increases leakage pathways.
Innovation Solution
The use of solid state doping sources, like borosilicate glass (BSG) and phosphosilicate glass (PSG), is employed to selectively dope sub-fin regions of tri-gate transistors, allowing for low-doped fins with high-doped sub-fin regions, thereby improving carrier mobility and reducing leakage while maintaining precise doping control through recessed doping layers and drive-in anneals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional doping methods are used to fabricate multi-gate transistors, then device dimensions can be scaled down, but high doping levels in fin regions increase ionized impurity scattering and random variation in threshold voltage
Solution Approach 1:
The fin structure is segmented into two distinct regions: the fin channel region and the sub-fin region. Each region receives different doping treatments through selective masking and doping processes, allowing the fin channel to maintain low doping levels for reduced threshold voltage variation while the sub-fin region receives higher doping for leakage suppression.
Solution Approach 2:
Different doping concentrations are applied to different spatial locations within the transistor structure. The fin channel region maintains low doping concentration to minimize ionized impurity scattering and threshold voltage random variation, while the sub-fin region receives high doping concentration to suppress leakage pathways, creating locally optimized electrical properties.
2Length of moving object
If conventional doping methods are used, then device dimensions can be scaled down, but carrier mobility is degraded due to increased ionized impurity scattering
Solution Approach 1:
The fin structure is segmented into the fin channel region and sub-fin region, with selective doping applied to each. The fin channel region maintains low doping levels to preserve carrier mobility and reduce ionized impurity scattering, while the sub-fin region receives high doping for leakage suppression.
Solution Approach 2:
Low doping concentration is applied locally to the fin channel region to minimize ionized impurity scattering and maintain high carrier mobility, while high doping concentration is applied locally to the sub-fin region to suppress leakage, creating spatially differentiated electrical properties.
3Length of moving object
If conventional doping methods are used, then device dimensions can be scaled down, but leakage pathways are increased
Solution Approach 1:
The fin structure is segmented into fin channel and sub-fin regions with different doping levels. The sub-fin region receives high doping concentration specifically targeted at suppressing leakage pathways between source and drain, while the fin channel maintains low doping for optimal transistor performance.
Solution Approach 2:
High doping concentration is applied locally to the sub-fin region to suppress leakage pathways and improve device reliability, while the fin channel region maintains low doping concentration to preserve carrier mobility and reduce threshold voltage variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances current drive and reduces random mismatch in threshold voltage, enabling operation at lower voltages without functional failures while preventing sub-fin source-drain leakage, by confining dopants to sub-fin regions and maintaining low doping in the fin channels.
Implementation Method 1
driving dopants from the solid state dopant source layer into the sub-fin regions
Implementation Method 2
The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions
Data Source
AI summary
Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.