Sub-lithographic Charge Storage Elements via Spacer Patterning
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high device densities due to the need for smaller feature sizes and close spacing between elements, which requires sophisticated manufacturing techniques and is limited by photolithography resolution.
Innovation Solution
A method of forming a sub-lithographic charge storage element on a semiconductor substrate using spacer formation techniques, where a first layer with a greater height than the second layer is used, and a spacer is formed adjacent to the side surface and upper surface of the second layer, allowing for the removal of exposed portions of the second layer to create a narrow charge storage element, independent of photolithography limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If photolithography techniques are used to create smaller features, then device density is improved, but manufacturing complexity and difficulty increase due to resolution limitations
Solution Approach 1:
The patent transitions from planar photolithography patterning to three-dimensional spacer-based patterning. By forming spacers on the sidewalls of mandrels and using vertical dimension control (spacer thickness) to define horizontal feature dimensions, the method achieves sub-lithographic precision without being constrained by optical resolution limits.
Solution Approach 2:
The patent introduces spacers as intermediary structures that mediate between the lithographically-defined mandrels and the final charge storage elements. The spacers serve as self-aligned masks that protect portions of the second layer during etching, enabling precise feature definition through a intermediate patterning step rather than direct photolithography.
2Area of stationary object
If feature sizes are reduced to increase device density, then packing density is improved, but manufacturing difficulty increases due to sophisticated techniques required
Solution Approach 1:
The patent performs preliminary actions by forming the first layer with protruding portions and depositing spacer material before the final etching step. This preliminary structuring creates self-aligned patterns that guide subsequent processing, simplifying the overall manufacturing sequence compared to direct multi-step lithography approaches.
Solution Approach 2:
The spacers serve as self-aligned masks that automatically define the pattern locations based on the mandrel geometry. The etching process self-organizes around the spacer structures, creating charge storage elements with precise dimensions without requiring additional alignment steps or complex photolithography procedures.
3Area of stationary object
If close spacing between elements is achieved to increase device density, then device packing is improved, but manufacturing precision requirements increase beyond photolithography capabilities
Solution Approach 1:
The patent controls horizontal spacing between elements by controlling the vertical thickness of spacer deposits. The spacer thickness, determined by conformal deposition parameters rather than optical exposure, directly defines the spacing between adjacent charge storage elements, achieving sub-lithographic spacing precision through dimensional transformation.
Data Source
AI summary
A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.