Sub-Resolution Alignment Mark for Semiconductor Patterning
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Solution Overview
Problem
Traditional semiconductor fabrication methods face challenges in achieving small geometry sizes and small pitch sizes due to increased complexity, higher costs, and alignment errors, particularly as geometry sizes shrink, leading to issues like 'disappearing' large patterns and the need for additional photomasks and processes.
Innovation Solution
The use of a specific alignment mark design with sub-resolution patterns and a spacer patterning technique that forms spacers around alignment marks to maintain pattern integrity without requiring additional photomasks, allowing for efficient formation of small device geometries and pitches without losing large pattern shape or requiring extra processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photomasks are used to pattern a wafer to achieve small geometry sizes and small pitch sizes, then manufacturing precision is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The alignment mark is segmented into multiple sub-resolution patterns arranged in a specific geometric configuration. This segmentation allows the alignment mark to provide sufficient alignment information while maintaining a compact size that prevents it from disappearing during spacer patterning, thereby reducing the need for multiple photomasks
Solution Approach 2:
The invention transitions from using large, single-dimension alignment marks to using sub-resolution patterns arranged in a multi-dimensional geometric configuration. This dimensional transformation allows the alignment mark to maintain integrity during spacer patterning while providing adequate alignment signals, eliminating the need for additional photomasks
2Manufacturing precision
If multiple photomasks are used to pattern a wafer to achieve small pitch sizes, then manufacturing precision is improved, but fabrication time increases
Solution Approach 1:
The alignment mark is divided into multiple sub-resolution patterns that can be formed in a single photolithography step. This segmentation enables the alignment mark to provide sufficient alignment information while maintaining a compact size that prevents disappearance during spacer patterning, thereby reducing fabrication time by eliminating additional photomask steps
3Manufacturing precision
If traditional alignment mark designs are used with spacer patterning, then small device geometries can be formed, but large patterns disappear or lose their shape
Solution Approach 1:
The alignment mark uses sub-resolution patterns with specific local geometric qualities arranged in a configuration that maintains overall pattern integrity. The local sub-resolution features provide adequate alignment signals while the global geometric arrangement prevents the pattern from disappearing during spacer patterning, thus maintaining both small device geometries and large pattern shape
4Shape
If additional photomasks are used to protect alignment marks during spacer patterning, then pattern integrity is maintained, but fabrication cost and complexity increase
Solution Approach 1:
The alignment mark is segmented into sub-resolution patterns with a compact geometric configuration that inherently maintains pattern integrity during spacer patterning without requiring additional photomasks. This segmentation allows the alignment mark to provide sufficient alignment information while preventing disappearance, thereby maintaining pattern integrity and reducing fabrication complexity
Solution Approach 2:
The sub-resolution patterns act as an intermediary structure that provides alignment information while preventing the alignment mark from disappearing during spacer patterning. This intermediary design eliminates the need for additional protective photomasks, maintaining pattern integrity while reducing fabrication process complexity
Data Source
AI summary
Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance.