3D Semiconductor Memory Sub-Block Erasing via Voltage Isolation
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Solution Overview
Problem
Existing nonvolatile memory devices face inefficiencies in data erasure, particularly when increasing the number of cell strings in memory blocks, leading to prolonged erase times and reduced memory efficiency.
Innovation Solution
The implementation of a nonvolatile memory device architecture that divides memory blocks into sub-blocks, allowing for erase operations to be performed by unit of sub-block, thereby improving erase efficiency and memory efficiency by quickly erasing data of small capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of cell strings in memory blocks is increased to improve memory capacity, then memory capacity is improved, but erase time is prolonged and memory efficiency is reduced
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block and second sub-block), each with independent control lines (first erase prevention line and second erase prevention line). This segmentation allows selective erasure of specific sub-blocks, enabling the erase operation to be performed more efficiently on smaller portions of the memory block rather than erasing the entire block, thus reducing overall erase time while maintaining high memory capacity.
2Ease of operation
If erase operation is performed on the entire memory block, then all data is erased, but time consumption increases and efficiency decreases when only partial erasure is needed
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block and second sub-block), each with independent control lines (first erase prevention line and second erase prevention line). This segmentation allows selective erasure of specific sub-blocks, enabling the erase operation to be performed more efficiently on smaller portions of the memory block rather than erasing the entire block, thus reducing overall erase time while maintaining high memory capacity.
Solution Approach 2:
Different erase prevention voltages are applied to different sub-blocks based on the erasure requirements. The first erase prevention line receives a first erase prevention voltage while the second erase prevention line receives a second erase prevention voltage, allowing localized control of erasure operations in different regions of the memory block, thereby improving erase efficiency when only partial erasure is needed.
3Productivity
If sub-block division is implemented to enable partial erasure, then erase efficiency is improved, but device complexity increases due to additional control lines
Solution Approach 1:
The memory block is divided into multiple sub-blocks (first sub-block and second sub-block), each with independent control lines (first erase prevention line and second erase prevention line). This segmentation allows selective erasure of specific sub-blocks, enabling the erase operation to be performed more efficiently on smaller portions of the memory block rather than erasing the entire block, thus reducing overall erase time while maintaining high memory capacity.
Solution Approach 2:
The erase prevention lines serve multiple functions: they act as control lines for selective sub-block erasure, provide voltage isolation between adjacent sub-blocks, and enable both partial and full erasure operations. This multi-functionality reduces the need for additional dedicated control structures, thereby limiting the increase in device complexity while achieving improved erase efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster and more efficient data erasure by applying specific voltages to selected and unselected sub-blocks, preventing unwanted erasure of unselected sub-blocks, thus enhancing memory efficiency and integration.
Implementation Method 1
an erase preventing voltage is applied to an erase prevention line included in an unselected sub block
Implementation Method 2
an erase preventing voltage is applied to a drain select line of an unselected sub block
Implementation Method 3
an erase preventing voltage is applied to gates of erase prevention transistors of cell strings included in an unselected sub block
Data Source
AI summary
A nonvolatile memory device includes well regions formed in a substrate and arranged in a first direction; a memory block including sub blocks which are formed over the substrate and correspond to the well regions, respectively; and bit lines disposed over the memory block, and extending in the first direction. Each of the sub blocks includes channel layers which are formed in a vertical direction between a corresponding well region and the bit lines, word lines and at least one drain select line and at least one erase prevention line, which are stacked over the substrate along the channel layers. In an erase operation, an erase voltage is applied to a well region corresponding to a selected sub block and an erase preventing voltage is applied to an erase prevention line included in an unselected sub block, the erase voltage may be prevented from being transferred to the unselected sub block.