Sub-Pixel Driving Circuit Layout for High-Density Display Substrates

The patent applies dimensionality change by transitioning from traditional horizontal layout to vertical stacking of transistor components. The first and second transistors are arranged in a vertical sequence along the first direction, with their active layers, gate electrodes, and source/drain regions stacked one above another. This vertical arrangement充分利用 the third dimension (vertical height) to accommodate multiple transistor components within the same horizontal footprint, thereby increasing pixel density without sacrificing layout space.

The patent implements nesting by placing the second transistor within the vertical space occupied by the first transistor. The second transistor's active layer is positioned above the first transistor's active layer, and its gate electrode is formed above the first transistor's gate electrode. This nested configuration allows multiple transistor components to share the same horizontal region while occupying different vertical levels, effectively maximizing the utilization of available layout space.

The patent introduces intermediary structures including first and second insulating layers positioned between the first and second transistors, as well as first and second shielding patterns formed at different heights. These intermediary elements act as electrical barriers and shields that isolate the electric fields of the tightly packed transistors, preventing signal interference while allowing the transistors to maintain close vertical proximity for space-efficient layout.

The patent applies local quality by implementing position-specific shielding measures. The first shielding pattern is formed at a first height above the first transistor, while the second shielding pattern is formed at a second height above the second transistor. This localized shielding approach provides targeted electromagnetic interference protection at critical locations where signal interference would otherwise occur, allowing tight packing without compromising signal integrity.

The patent applies segmentation by dividing the transistor structure into distinct vertical segments. The first transistor and second transistor are segmented into separate active layers, gate electrodes, and source/drain regions at different vertical levels. This segmentation allows each component to be independently fabricated and positioned, simplifying the manufacturing process despite the vertical stacking arrangement. The first insulating layer and second insulating layer further segment the structure into manageable sections.

The patent implements preliminary action by forming the first insulating layer and second insulating layer before depositing subsequent transistor components. The first gate insulating layer is formed after the first gate electrode, and the second gate insulating layer is formed after the second gate electrode. This preliminary formation of insulating layers establishes the vertical separation and electrical isolation needed for the stacked configuration, guiding subsequent fabrication steps and reducing overall layout complexity.