Sub-Pixel Electrode Layout to Reduce Display Parasitic Capacitance
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Solution Overview
Problem
Current display devices face challenges in achieving improved reliability, particularly in the design and arrangement of sub-pixels and alignment electrodes, which affect the overall performance and efficiency of light emission.
Innovation Solution
The proposed display device includes a configuration of first, second, and third sub-pixels with specific transistor arrangements, bridge patterns, and alignment electrodes, where the second alignment electrode is supplied with a low potential voltage and overlaps the bridge pattern, enhancing electrical connections and reducing parasitic capacitance between sub-pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second alignment electrode is supplied with a low potential voltage and overlaps the bridge pattern, then parasitic capacitance between sub-pixels is reduced and electrical connections are improved, but the device complexity increases due to additional electrode configurations and voltage supply requirements
Solution Approach 1:
The alignment electrodes are divided into multiple segments (first alignment electrode and second alignment electrode) with different voltage potentials. The second alignment electrode is supplied with a low potential voltage while the first alignment electrode maintains a different potential, creating distinct electrical zones that reduce parasitic capacitance between adjacent sub-pixels while maintaining structural organization.
Solution Approach 2:
The second alignment electrode is configured to overlap the bridge pattern in the planar dimension, creating a three-dimensional electrical field arrangement. This spatial overlap configuration allows the electrode to effectively reduce parasitic capacitance through vertical field distribution while maintaining a relatively simple planar layout.
2Reliability
If the second alignment electrode overlaps the bridge pattern, then electrical connections between sub-pixels are enhanced, but manufacturing precision requirements increase due to alignment constraints
Solution Approach 1:
The bridge pattern is designed and positioned in advance during the manufacturing process to serve as a predetermined alignment reference. The second alignment electrode is then configured to overlap this pre-established bridge pattern, which simplifies the alignment process by providing a fixed reference structure that guides the electrode positioning without requiring complex real-time alignment adjustments.
Solution Approach 2:
The bridge pattern functions as an intermediary structure that mediates between the underlying transistor source electrode and the second alignment electrode. This intermediate element provides a stable, pre-formed connection point that facilitates reliable electrical connection while reducing the direct alignment precision requirements between the alignment electrode and the deeper circuit elements.
Data Source
AI summary
A display device may include first, second, and third sub-pixels. Each of the first, second, and third sub-pixels may include: a pixel circuit layer including first, second, and third transistors disposed on a substrate, and a bridge pattern disposed on a gate electrode of the first transistor and a source electrode of the second transistor, a first end of the bridge pattern is electrically connected to the source electrode of the second transistor and a second end of the bridge pattern is electrically connected to the gate electrode of the first transistor; first and second alignment electrodes disposed on the pixel circuit layer; and light emitting elements disposed on the first and second alignment electrodes and electrically connected to at least one of the first, second, and third transistors. The second alignment electrode may be supplied with a low potential voltage and overlap the bridge pattern in a plan view.