Sub-Sampling PLL Phase Tracking for Wide Frequency Acquisition
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Solution Overview
Problem
Conventional sub-sampling phase lock loops (PLLs) face limitations in frequency tracking and capture range due to the absence of frequency discrimination capabilities in their phase detectors, leading to restricted bandwidth and jitter performance.
Innovation Solution
A modified sub-sampling phase lock loop architecture that incorporates samplers, a phase detector, and a processing unit to select and track phases based on predetermined criteria, enabling the detection of frequency errors and providing an infinite frequency capture range by determining frequency information through differential analysis of sampled values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional charge pump PLL with feedback divider is used, then frequency tracking capability is provided, but output noise increases due to charge pump noise multiplication by N^2
Solution Approach 1:
The patent extracts and removes the feedback divider from the PLL architecture, eliminating the source of noise multiplication. The frequency tracking function is then achieved through an alternative mechanism using multiple samplers and phase detectors that directly compare phases without requiring frequency division, thereby avoiding the N^2 noise multiplication problem while maintaining frequency tracking capability.
Solution Approach 2:
The patent employs multiple samplers that can operate in different modes to achieve both phase detection and frequency tracking functions simultaneously. The same sampler structure serves multiple purposes: phase comparison, frequency discrimination, and acquisition, eliminating the need for separate feedback divider circuitry and reducing overall system noise.
2Object-generated harmful factors
If a sub-sampling phase detector is used to reduce in-band phase noise, then reference spur is reduced, but frequency capture range becomes very limited
Solution Approach 1:
The patent segments the frequency detection function into multiple independent phase detectors, each comparing the input signal with differently phased reference signals. By combining the outputs of these segmented detectors, the system achieves both low phase noise (through sub-sampling) and wide frequency capture range (through multiple detection channels), resolving the contradiction between noise performance and adaptability.
Solution Approach 2:
The patent adds a temporal dimension to phase detection by using multiple samplers operating at different phases and combining their outputs over time. This multi-dimensional approach allows the system to extract both phase and frequency information while maintaining low noise characteristics, expanding the frequency capture range without sacrificing noise performance.
3Object-generated harmful factors
If sub-sampling PLL without feedback divider is used, then in-band phase noise is reduced to low values, but frequency acquisition requires separate acquisition loop
Solution Approach 1:
The patent merges the frequency acquisition function with the main phase-locked loop by integrating multiple phase detectors and samplers that simultaneously perform both acquisition and tracking functions. This unified architecture eliminates the need for a separate frequency acquisition loop, reducing system complexity while maintaining low in-band phase noise through the sub-sampling technique.
Data Source
AI summary
A sub-sampling phase lock loop includes samplers that obtain sampled values by sampling clock signal phases corresponding to a clock signal generated by a voltage controlled oscillator at sampling edges of reference signal phases of a reference signal generated by a reference clock generator over a reference clock cycle; and a phase detector that selects a phase for a particular instant of the reference signal based on at least one sampled value satisfying a predetermined criteria, the phase corresponding to a clock signal phase value and a reference signal phase value respectively selected from the clock signal and reference signal phases, the phase detector tracks the selected phase at every successive instant of the reference signal, and determines a sampled value associated with the selected phase in every successive instant of the reference signal; and a processing unit that acquires frequency information based on the tracking of the selected phase.