Packaging Substrate Conductive Post Alignment Layer

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Solution Overview

Problem

Conventional packaging substrates face challenges in achieving high electronic element mounting density and wiring density due to the complexity of electroplating processes and increased area consumption caused by large height-width ratios of conductive posts, which complicates the fabrication process and reduces available space for wiring.

Innovation Solution

The solution involves forming conductive structures with a first conductive portion, a conductive post, an alignment layer, and a conductive via, where the alignment layer has a vertical projection area larger than the conductive post and via, allowing for sufficient alignment tolerance without increasing the area consumption of the conductive post and first conductive portion, thereby increasing wiring and electronic element mounting density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the height of conductive posts is increased to embed capacitors, then the capacitor embedding capability is improved, but the electroplating effect deteriorates due to large height-width ratio

Engineering Contradiction:
Improvecapacitor embedding capabilityVSAvoidelectroplating effect
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The conductive post is divided into multiple segments (first conductive portion, second conductive portion, third conductive portion) formed through separate electroplating processes. This segmentation allows each segment to be formed with optimal electroplating parameters, avoiding the poor electroplating effect that would occur with a single tall post, while still achieving the required total height for capacitor embedding.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If the area of first conductive portion is increased to provide alignment tolerance, then the alignment tolerance is improved, but the wiring space deteriorates

Engineering Contradiction:
Improvealignment toleranceVSAvoidwiring space
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent introduces vertical layering (z-dimension) by forming multiple conductive portions at different heights and positions. The first conductive portion can be smaller in area since alignment tolerance is provided through the vertical stacking arrangement and the larger area of upper conductive portions, rather than requiring a large base area. This dimensional transition resolves the conflict between alignment tolerance and wiring space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Volume of moving object

If multiple electroplating processes are used to form conductive post portions, then the capacitor embedding capability is improved, but the fabrication process complexity deteriorates

Engineering Contradiction:
Improvecapacitor embedding capabilityVSAvoidfabrication process complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The conductive post is divided into multiple segments (first conductive portion, second conductive portion, third conductive portion) formed through separate electroplating processes. This segmentation allows each segment to be formed with optimal electroplating parameters, avoiding the poor electroplating effect that would occur with a single tall post, while still achieving the required total height for capacitor embedding.

Inventive Principle:
Principle #1Segmentation

4Manufacturing precision

If the area of first conductive portion is increased to provide alignment tolerance, then the alignment tolerance is improved, but the wiring density deteriorates

Engineering Contradiction:
Improvealignment toleranceVSAvoidwiring density
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent introduces vertical layering (z-dimension) by forming multiple conductive portions at different heights and positions. The first conductive portion can be smaller in area since alignment tolerance is provided through the vertical stacking arrangement and the larger area of upper conductive portions, rather than requiring a large base area. This dimensional transition resolves the conflict between alignment tolerance and wiring space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces area consumption and enhances wiring density and electronic element mounting density by providing sufficient alignment tolerance, simplifying the fabrication process and improving product yield.

Implementation Method 1

The first post portion 121 and the second post portion 122 are formed through separate electroplating processes

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS9265154B2Packaging substrate and fabrication method thereof
Publication Date: 2016.02.16 SILICONWARE PRECISION IND CO LTD
  • US9265154B2 patent drawing
  • US9265154B2 patent drawing
  • US9265154B2 patent drawing

AI summary

A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.