Substrate With Equal Area Conductive Elements For Die Parallelism
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor packages, the arrangement of bump pads, traces, and vias creates a long electrical path that occupies a large area on the substrate, leading to uneven solder wetting and potential die tilting due to differences in solder height on bump pads and vias, which affects the package's parallelism and electrical performance.
Innovation Solution
A substrate design featuring a first conductive element that does not extend through the dielectric layer and a second conductive element that does, with the upper surfaces of both elements having equal areas, allowing for equal solder volume distribution and improved die parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conductive via extends through the substrate with a bump pad and trace arrangement, then electrical connection between opposite surfaces is achieved, but the electrical path length increases and occupies large area
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement (bump pad → trace → via) to a three-dimensional vertical arrangement where the conductive element extends through the substrate thickness. This dimensional change allows electrical connection while minimizing surface area occupation and reducing the effective electrical path length through direct vertical coupling.
Solution Approach 2:
The patent merges the bump pad and via into a single integrated conductive element that extends continuously through the substrate. This consolidation eliminates the need for separate trace connections and reduces the overall electrical path length while maintaining reliable electrical connection between opposite surfaces.
2Reliability
If bump pad and via have different areas, then electrical connection is established, but solder height becomes uneven causing die tilting
Solution Approach 1:
The patent makes the upper surface area of the via equal to the bump pad area, creating homogeneous solder receptacle surfaces. This ensures uniform solder height when the same solder volume is used, preventing die tilting and maintaining manufacturing precision for die parallelism.
Solution Approach 2:
By equalizing the surface areas of the bump pad and via, the patent creates equipotential solder surfaces that receive identical solder volumes to produce equal solder heights. This eliminates the potential difference in solder levels that would otherwise cause die tilting.
3Reliability
If trace and via are arranged separately, then electrical connection path is formed, but the area occupied on the substrate increases
Solution Approach 1:
The patent combines the bump pad and via into a single continuous conductive element, eliminating the need for separate trace structures. This merging reduces the total area occupied on the substrate while maintaining reliable electrical connection between opposite surfaces.
Solution Approach 2:
The patent moves the electrical connection path from a two-dimensional surface layout (requiring trace routing) to a three-dimensional vertical path through the substrate. This dimensional transition eliminates the need for lateral trace connections and minimizes substrate area occupation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the length of the electrical path, ensures uniform solder height, and maintains the die parallel to the substrate, enhancing electrical performance and allowing for more dense routing and increased I/O capability.
Implementation Method 1
forming a plurality of through holes in the dielectric layer corresponding to the openings of the mask layer by laser drilling
Data Source
AI summary
A substrate includes a dielectric layer having a first surface and a second surface opposite to the first surface, a first circuit layer and at least one second conductive element. The first circuit layer is disposed adjacent to the first surface of the dielectric layer, and includes at least one trace and at least one first conductive element connected to the trace. The first conductive element does not extend through the dielectric layer. The second conductive element extends through the dielectric layer. An area of an upper surface of the second conductive element is substantially equal to an area of an upper surface of the first conductive element.