Substrate-Free Semiconductor Packaging via Redistribution Layer
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Solution Overview
Problem
Current semiconductor packaging techniques require organic substrates, which are costly and have a large form factor, limiting the integration density and efficiency of electronic components.
Innovation Solution
The use of a redistribution layer (RDL) and molding compounds to package semiconductor devices without a substrate, allowing for lateral or vertical integration of multiple ICs with z-axis connections such as wire bonds, solder balls, or metal pillars, and x-y connections in a metallization layer, eliminating the need for a substrate and enabling more efficient packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If organic substrates are used in semiconductor packaging, then structural support and electrical connections are provided, but manufacturing cost increases and form factor enlarges
Solution Approach 1:
The patent extracts and eliminates the organic substrate from the packaging structure, retaining only the essential functions of support and connection through alternative means (molding compound and metallization layers). This removal directly reduces both cost and form factor while maintaining packaging functionality.
Solution Approach 2:
The patent merges the functions of substrate support, electrical connection, and packaging protection into an integrated structure using molding compound and metallization layers. This consolidation eliminates the need for separate organic substrate components, reducing overall form factor and manufacturing complexity.
2Ease of manufacture
If organic substrates are used in semiconductor packaging, then structural support is provided, but manufacturing cost increases
Solution Approach 1:
The patent removes the organic substrate while replacing its structural support function with the molding compound and metallization layer assembly. This substitution maintains necessary mechanical strength and support without incurring substrate manufacturing costs.
Solution Approach 2:
The patent employs a composite structure combining molding compound and metallization layers to provide structural support previously delivered by organic substrates. This composite approach achieves equivalent or superior mechanical properties at lower cost.
3Productivity
If traditional packaging techniques are used, then electrical connections are established, but integration density decreases
Solution Approach 1:
The patent transitions from planar electrical connections to three-dimensional vertical connections using z-axis bonding techniques. This dimensional change enables higher integration density by stacking components vertically rather than only arranging them laterally, effectively increasing productivity.
Solution Approach 2:
The patent segments the packaging structure into distinct functional layers (molding compound, metallization layers, bonded interfaces) that can be independently optimized and manufactured. This segmentation enables more efficient resource utilization and higher integration density while managing complexity through modular design.
Data Source
AI summary
Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.