Substrate-Less Flip-Chip LED Package for Uniform White Light
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Solution Overview
Problem
Tight footprint white light emitting diode (LED) packages face limitations due to vertical emission profile constraints, phosphor thickness non-uniformity leading to poor color uniformity, and heat-induced degradation of the phosphor layer, exacerbated by poor heat dissipation and low yield in wafer level substrate lift-off processes, especially with larger substrates.
Innovation Solution
A small footprint, low profile white lateral flip-chip LED package is developed where the substrate is removed and coated with a conforming phosphor layer, allowing for minimal side emission and direct heat dissipation, with the phosphor layer supported by the chip and underfill material, enabling scalable wafer-level processing and improved color uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If phosphor is conformally coated on the vertical sidewall of LED chips, then all light is captured, but phosphor thickness non-uniformity results in poor goniometric color uniformity
Solution Approach 1:
The patent extracts the substrate from the LED chip structure, creating a substrate-less LED chip that is then bonded to a submount. This extraction eliminates the need for conformal sidewall phosphor coating, allowing instead for a planar phosphor coating on the chip top surface, which achieves uniform phosphor thickness and excellent color uniformity while maintaining high light capture efficiency through the optimized chip-submount configuration.
2Illumination intensity
If phosphor blend is coated close to the chip to capture all light, then light capture efficiency is improved, but heat-induced degradation of the host material occurs due to absorbed radiometric power
Solution Approach 1:
The patent moves the phosphor coating from a vertical sidewall configuration to a horizontal planar configuration on the chip top surface. This dimensional change allows the phosphor to be positioned close to the light source for efficient light capture while the heat can dissipate laterally through the chip and submount structure, preventing heat-induced degradation of the phosphor host material.
3Productivity
If wafer level substrate lift-off is performed, then manufacturing efficiency is improved, but yield is very low due to epitaxial layer cracking after lift-off
Solution Approach 1:
The patent extracts the substrate at the wafer level before die bonding, creating substrate-less LED chips that are directly bonded to the submount. This extraction approach eliminates the substrate lift-off process entirely, avoiding epitaxial layer cracking and achieving high manufacturing yield while maintaining high productivity through efficient wafer-level processing.
4Illumination intensity
If multiple LED chips are used to achieve white light output, then light output is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple LED chips and the submount into a single integrated package structure at the wafer level. Multiple substrate-less LED chips are bonded in close proximity to a common submount with integrated phosphor coating, creating a unified white LED package that achieves high light output while minimizing device complexity through consolidated manufacturing and compact design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution results in a high lumen per unit area, cost-effective, and high-yield light source with enhanced color uniformity and efficient heat dissipation, suitable for high-volume production and thin film processing.
Implementation Method 1
a conforming layer of phosphor or phosphor blend... coated with a conforming phosphor layer
Implementation Method 2
provides for direct heat dissipation of phosphor layer from thermally conductive LED epitaxial layer after substrate removal
Data Source
AI summary
A surface mount LED package having a tight footprint and small vertical image size is fabricated by a method comprising: forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing; forming electrical vias in a sub mount, the electrical vias passing from a front side of the sub-mount to a back-side of the sub-mount; flip chip bonding the light emitting diode chips on the front-side of the sub mount such that each light emitting diode chip electrically contacts selected electrical vias; thinning or removing the substrates of the flip-chip bonded light emitting diode chips; and after the thinning, disposing a phosphor over the flip chip bonded light emitting diode chips.


