Package Substrate Lid Structure for Heat Dissipation and Glass Protection

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Solution Overview

Problem

Conventional package substrates suffer from limited heat dissipation characteristics, leading to reduced reliability and mechanical vulnerability, especially with the use of glass substrates, which can be damaged during processing and integrated circuits face electrical defects due to poor thermal management.

Innovation Solution

A substrate with a specially designed lid structure featuring a glass base and a lid structure that includes an accommodation space and a frame, divided into inner and outer regions, with enhanced thermal conductivity and mechanical properties, incorporating a redistribution layer and side closing portions to protect and dissipate heat effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a wire is exposed to form a wire bonding pad, then wire bonding can be performed, but the bonding pad occupies additional chip area and increases the number of chip formation processes

Engineering Contradiction:
Improvewire bonding capabilityVSAvoidchip area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent combines the bonding pad function with the lead frame structure by forming the bonding pad on the lead frame body rather than exposing a separate wire on the chip. This integration eliminates the need for additional chip area dedicated to bonding pads and reduces the number of chip formation processes while maintaining wire bonding capability.

Inventive Principle:
Principle #5Merging (Combining)

2Ease of manufacture

If a bonding pad is formed on the chip, then wire bonding can be performed, but the number of chip formation processes increases

Engineering Contradiction:
Improvewire bonding capabilityVSAvoidnumber of chip formation processes
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The bonding pad is formed on the lead frame body during lead frame processing rather than as a separate step on the chip. This merging of functions reduces the number of chip formation processes while enabling wire bonding.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The lead frame body serves as an intermediary structure that provides the bonding pad function, eliminating the need for direct bonding pad formation on the chip and thereby reducing process complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the lead frame body has a large area, then it can serve as an effective bonding pad, but the overall package size increases

Engineering Contradiction:
Improvebonding pad effectivenessVSAvoidpackage size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The lead frame body is designed with localized bonding pad regions that have the necessary electrical and mechanical properties for effective wire bonding, while other areas maintain their structural functions. This localized approach ensures bonding effectiveness without requiring the entire lead frame body to be enlarged.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The lead frame body serves multiple functions simultaneously: it provides structural support, electrical connection, and bonding pad functionality. This multi-functionality eliminates the need for separate bonding pad structures and reduces overall package size while maintaining bonding effectiveness.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4158686B1Substrate comprising a lid structure, package substrate comprising the same and semiconductor device
Publication Date: 2026.04.15 ABSOLICS INC
  • EP4158686B1 patent drawingFigure 1A~1B
  • EP4158686B1 patent drawingFigure 2A~2B
  • EP4158686B1 patent drawingFigure 3A~3B

AI summary

Example embodiments provide a package substrate including a lid structure. The package substrate includes a substrate, a semiconductor element arranged on one surface of the substrate, and a lid surrounding at least a portion of the semiconductor element with an accommodation space for housing the element and a frame surrounding a portion of the accommodation space. The lid includes an inner and outer region. The outer region of the lid extends outwardly beyond the outer periphery of the substrate.