Substrate Package Layout for High-Data-Rate Signal Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional signal routing on printed circuit boards (PCBs) is inadequate for high data rate, high bandwidth, and high port applications, leading to signal integrity issues and increased substrate size due to the use of co-package-copper (CPC) and co-package-optics (CPO) components that occupy valuable space and interfere with heat dissipation.
Innovation Solution
Positioning signal routing components, such as CPC and CPO, on the opposite side of the substrate from the die, allowing for a compact form factor and efficient heat dissipation by housing the die and routing components on opposite sides, with a heatsink or cold plate for thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CPC or CPO components are positioned on the substrate periphery to enable high data rate signal routing, then signal integrity is improved, but substrate size increases and heat dissipation is interfered with
Solution Approach 1:
The patent positions CPC/CPO components on the opposite side of the substrate from the die, utilizing the z-dimension (vertical stacking) rather than expanding in the x-y plane. This allows high data rate signal routing through the substrate thickness, maintaining compact substrate footprint while achieving improved signal integrity through dedicated high-speed routing paths.
Solution Approach 2:
The substrate is divided into two functional sides: one side hosts the die and its associated cooling mechanisms, while the opposite side hosts the CPC/CPO components and their routing paths. This segmentation separates heat-generating elements from signal-sensitive elements, allowing independent optimization of both thermal management and signal integrity without increasing overall substrate area.
2Reliability
If CPC or CPO components are positioned on the substrate periphery to enable high data rate signal routing, then signal integrity is improved, but heat dissipation mechanism is interfered with
Solution Approach 1:
The substrate is divided into two functional sides: one side hosts the die and its associated cooling mechanisms, while the opposite side hosts the CPC/CPO components and their routing paths. This segmentation separates heat-generating elements from signal-sensitive elements, allowing independent optimization of both thermal management and signal integrity without increasing overall substrate area.
Solution Approach 2:
The patent extracts the CPC/CPO components from the same plane as the die and positions them on the opposite side of the substrate. This extraction removes the interference between cooling mechanisms and signal routing components, allowing the cooling system to operate without obstruction while maintaining compact substrate dimensions.
3Area of stationary object
If conventional PCB signal routing is used, then substrate size is reduced, but signal integrity deteriorates for high data rate applications
Solution Approach 1:
The patent positions CPC/CPO components on the opposite side of the substrate from the die, utilizing the z-dimension (vertical stacking) rather than expanding in the x-y plane. This allows high data rate signal routing through the substrate thickness, maintaining compact substrate footprint while achieving improved signal integrity through dedicated high-speed routing paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains a compact substrate size, reduces signal loss, improves signal integrity, and enhances thermal performance by separating heat dissipation mechanisms from signal routing components.
Implementation Method 1
a heatsink or cold plate for thermal management
Implementation Method 2
a heatsink or cold plate for thermal management
Data Source
AI summary
A device includes a substrate having a first side and a second side, wherein the first side faces opposite the second side. The device also includes a die positioned on the second side of the substrate and electrically coupled to the substrate. The device includes a signal routing component positioned on the first side of the substrate. The signal routing component is configured to route signals between the die and an external component to the device through the substrate. The device includes an electrical board positioned on the second side of the substrate. The electrical board is electrically coupled to the substrate.


