Substrate Embedding Passive Element Via Segmentation
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Solution Overview
Problem
Existing substrate embedding technologies face limitations in reducing impedance in the current path between passive elements and other devices, hindering stable power supply to high-performance semiconductor chips.
Innovation Solution
A substrate design with a passive element embedded in an insulating layer, featuring a first via with a larger volume and cross-sectional area than a second via, and a height ratio of 0.5 to 1.5 times that of the second via, to enhance electrical connectivity and reduce impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via holes are used for electrical connection between embedded passive element and circuit patterns, then manufacturing process is simple, but impedance of current path cannot be sufficiently reduced
Solution Approach 1:
The via structure is segmented into two distinct parts: a first via hole extending from the lower surface through the insulating layer to contact the lower surface of the external electrode, and a second via hole extending from the upper surface to contact the upper surface of the external electrode. This segmentation allows each via to be optimized independently for impedance reduction while maintaining manufacturing feasibility.
Solution Approach 2:
Different regions of the via structure are assigned different properties: the first via hole has a larger cross-sectional area and extends deeper to reduce impedance at the lower connection point, while the second via hole has a smaller cross-sectional area at the upper connection point. This local differentiation optimizes impedance characteristics at each interface without requiring uniform complexity throughout.
2Reliability
If distance between decoupling capacitor and semiconductor chip is minimized, then power supply stability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The passive element is embedded in the insulating layer before the insulating layer is fully formed and before circuit patterns are created. This preliminary embedding action allows precise positioning of the passive element relative to where the semiconductor chip will be mounted, ensuring minimal distance and optimal power supply stability while maintaining manufacturing precision through controlled placement.
Data Source
AI summary
A substrate embedding a passive element includes a first conductor pattern layer disposed on a lower surface thereof and a second conductor pattern layer disposed on an upper surface thereof; a first via electrically connecting between the passive element and the first conductor pattern layer; and a second via electrically connecting between the passive element and the second conductor pattern layer, in which a volume of the first via is larger than that of the second via.