Processed Substrate Planarization for Dishing-Free Interconnect Bonding
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Solution Overview
Problem
The dual damascene process in semiconductor chip fabrication leads to substrate surface dishing and erosion due to the differences in mechanical properties between metal interconnects and dielectric materials, causing defects like shorting and reduced yield, and requiring complex bonding techniques for flat surfaces.
Innovation Solution
A method involving selective etching using fluoride and oxidizing agents with glycerol to control the etching process, allowing for the protrusion of conductive material above recessed regions without damaging the substrate, enabling bonding of substrates with improved flatness and interconnect coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dual damascene process is used to fabricate interconnect layers, then device density and yield are improved, but substrate surface dishing and erosion occur due to differences in mechanical properties between metal interconnects and dielectric materials
Solution Approach 1:
The patent applies preliminary action by performing a planarization process before the bonding step to pre-correct the dishing and erosion defects on the substrate surface. This preliminary planarization ensures that the bonding surfaces are sufficiently flat to achieve reliable hybrid bonding, thereby resolving the contradiction between maintaining high device density and achieving the required surface flatness for bonding.
2Productivity
If metal pattern density is increased to improve device performance, then device density is improved, but erosion increases in high metal pattern density features
Solution Approach 1:
The patent converts the harmful erosion effect into a beneficial outcome by selectively removing the eroded dielectric material through a planarization process. This planarization step eliminates the erosion defects while preserving the high-density metal interconnect patterns, thereby converting the previously harmful erosion into an opportunity to achieve a flat bonding surface that maintains both high device density and eliminates shorting defects.
3Reliability
If substrate surface flatness is improved through planarization, then bonding reliability is improved, but additional process steps are required
Solution Approach 1:
The patent merges the planarization function into the existing fabrication process flow by integrating it as a preparatory step before hybrid bonding. This merged approach combines the surface flatness correction with the bonding process sequence, achieving improved bonding reliability without requiring entirely separate or additional complex process equipment, thereby resolving the contradiction between reliability improvement and process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces substrate surface roughness and dishing, enhancing bonding reliability and yield by forming smooth, planar surfaces that allow for precise electrical coupling of interconnects across substrates.
Implementation Method 1
etching the surface of the processed substrate with an etchant to form a substantially planar surface on the processed substrate, with portions of the conductive material protruding above the substantially planar surface
Implementation Method 2
A method involving selective etching using fluoride and oxidizing agents with glycerol to control the etching process
Data Source
AI summary
Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.