Strip Level Substrate Solder Resist Patterning for Warpage Reduction

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Solution Overview

Problem

Conventional semiconductor package manufacturing processes experience early warpage phenomena due to the expansion and contraction of solder resist during the reflow process, leading to difficulties in processing and degradation of semiconductor packages.

Innovation Solution

The method involves applying and patterning solder resist on a strip level substrate, removing the resist on the scribe line in addition to the electrode terminals and ball lands, to minimize the amount of solder resist and prevent warpage, thereby simplifying and stabilizing the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If solder resist is applied on the front surface of the strip level substrate and patterned to expose electrode terminals and ball lands, then the manufacturing process is simplified, but the solder resist repeatedly expands and contracts during the reflow process causing early warpage phenomenon

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidsubstrate warpage

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The substrate is divided into multiple unit substrates arranged in a matrix structure, allowing parallel processing of multiple chips simultaneously. This segmentation enables the solder resist to be applied and patterned on each unit substrate independently, reducing the overall warpage impact while maintaining process simplicity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The solder resist is selectively applied only to specific regions where chips will be attached, rather than covering the entire substrate surface. This localized application reduces the total amount of solder resist material that undergoes thermal expansion and contraction, thereby minimizing the early warpage phenomenon while still providing necessary protection and electrical isolation.

Inventive Principle:

Principle #3Local quality

2Productivity

If multiple chips are attached simultaneously on a strip level substrate, then productivity is improved, but the warpage phenomenon affects the progress of subsequent processes and degrades package quality

Engineering Contradiction:

Improvemanufacturing throughputVSAvoidpackage quality

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The strip level substrate is divided into multiple unit substrates that can be processed simultaneously. Each unit substrate is treated as an independent processing unit with its own chip attachment, wire bonding, and molding processes. This segmentation allows high productivity through parallel processing while maintaining consistent quality across all units by isolating warpage effects to individual units rather than affecting the entire substrate.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The solder resist is applied and patterned on all unit substrates before chip attachment. This preliminary action ensures that the solder resist structure is established and stabilized before the chips are mounted, reducing the likelihood of warpage-induced defects during subsequent processing steps and ensuring consistent quality across all packages produced in parallel.

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If solder resist is applied on electrode terminals during flip chip package manufacturing, then the process is completed, but the reflow process causes warpage that complicates subsequent manufacturing steps

Engineering Contradiction:

Improveprocess completionVSAvoidprocess complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The solder resist is applied locally only to the electrode terminals and ball lands where chips will be attached, rather than covering the entire substrate. This selective application minimizes the amount of solder resist material that undergoes thermal cycling during reflow, reducing warpage while still providing necessary electrical isolation and protection. The reduced warpage simplifies subsequent manufacturing steps by maintaining better substrate flatness and dimensional stability.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the warpage phenomenon, enhancing the integrity and reliability of semiconductor packages by minimizing faulty operations and defects during the manufacturing process.

Implementation Method 1

the solder resist applied on the front surface of the strip level substrate repeatedly expands and contracts during the reflow process, causing an early warpage phenomenon on the strip level substrate

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS7595255B2Method for manufacturing strip level substrate without warpage and method for manufacturing semiconductor package using the same

Publication Date: 2009.09.29 SK HYNIX INC

AI summary

A strip level substrate is manufactured by: applying solder resist on a substrate including a plurality of unit substrate divided by a scribe line; and patterning the applied solder resist to expose an electrode terminal and a ball land in each unit substrate, wherein the patterning of the solder resist is performed to be removed together with a solder resist part applied on the scribe line in order to reduce an early warpage of the strip level substrate.