Substrateless Power Device Packages Using Solder Bumps and Molding
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Solution Overview
Problem
Conventional methods for handling and processing ultra-thin semiconductor wafers, especially those thinner than 1 mil, are prone to damage and breakage due to fragility, and existing techniques are not adequately designed to handle such thin wafers effectively, posing challenges in achieving desired features like reduced electrical resistance and minimal package thickness while ensuring wafer stability and efficient production.
Innovation Solution
A substrate-less power device package is achieved using a combination of solder bumping and wafer level molding, which provides mechanical support from the front side of the wafer, simplifying the process, reducing production costs, and being compatible with existing metal clip bonding assembly processes, while using solder bumps to replace through vias for better electrical conductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the wafer thickness is reduced to decrease on-resistance and package thickness, then the electrical resistance decreases, but the wafer becomes fragile and prone to damage during processing
Solution Approach 1:
The patent applies beforehand cushioning by depositing a metal layer on the back surface of the wafer before thinning processes. This metal layer serves as a protective cushion that prevents wafer breakage during subsequent processing steps while allowing the wafer to be thinned to ultra-thin dimensions (less than 1 mil) to achieve low on-resistance. The metal layer is deposited using conventional techniques such as sputtering or evaporation, and it provides mechanical support without significantly increasing the overall package thickness.
2Ease of manufacture
If conventional handling methods are used for ultra-thin wafers, then the processing can be simplified, but the risk of wafer damage increases significantly
Solution Approach 1:
The patent introduces an intermediary metal layer on the back surface of the wafer that acts as a mediator between the handling tools and the ultra-thin wafer. This metal layer enables conventional handling and processing equipment to work effectively with ultra-thin wafers by providing a robust interface for gripping and manipulating the wafer without directly contacting and potentially damaging the thin semiconductor substrate. The metal layer serves as a protective intermediary that allows simplified processing while maintaining wafer integrity.
3Length of stationary object
If the wafer is thinned to achieve minimal package thickness, then the package thickness is reduced, but the mechanical support and stability are compromised
Solution Approach 1:
The patent applies local quality by selectively depositing metal on the back surface of the wafer in specific patterns rather than uniformly across the entire surface. This localized metal deposition provides mechanical support and stability where needed (at the edges and connection points) while leaving the central active area thin for optimal electrical performance. The metal can be deposited in ring patterns, grid patterns, or other configurations that provide structural reinforcement without significantly increasing the overall package thickness, thus achieving minimal package thickness while maintaining mechanical strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient handling and processing of ultra-thin wafers, reduces the risk of damage, and achieves low on-resistance and minimal package thickness, while maintaining effective electrical characteristics, thus addressing the limitations of conventional methods.
Implementation Method 1
A substrate-less power device package is achieved using a combination of solder bumping and wafer level molding
Implementation Method 2
wafer level molding, which provides mechanical support from the front side of the wafer
Implementation Method 3
metal layer is deposited on a back surface of the substrate-less power device chip
Data Source
AI summary
A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.