Sub-Threshold FPGA Interconnect for Low-Energy Flexible Logic
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Solution Overview
Problem
Existing ultra-low power (ULP) devices face design complexity due to strict resource constraints, and current technologies fail to provide both flexibility and energy efficiency, with commercial processors and FPGAs being inefficient, while sub-threshold ASICs are inflexible and expensive for low-volume projects.
Innovation Solution
A sub-threshold FPGA design utilizing a low-swing, dual-VDD interconnect scheme, custom asynchronous sense amplifiers, and improved passgate interconnects to reduce area, energy, and delay, along with increased clustering and local routing to optimize energy efficiency and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If commercial processors and FPGAs are used, then flexibility is provided, but energy efficiency deteriorates
Solution Approach 1:
The patent operates the FPGA logic blocks and interconnect at sub-threshold voltage levels (below the transistor threshold voltage VT), fundamentally changing the operating voltage parameter to achieve ultra-low power consumption while maintaining flexibility through programmable logic blocks and routing
2Use of energy by moving object
If sub-VT ASICs are used, then energy efficiency is improved, but flexibility deteriorates
Solution Approach 1:
The patent implements a universal sub-threshold FPGA architecture where programmable logic blocks can be configured to perform multiple different logic functions, and the interconnect can route signals between any configurable blocks, providing both the energy efficiency of sub-VT operation and the flexibility of reconfigurable logic
3Adaptability or versatility
If conventional FPGA interconnect is used, then routing flexibility is provided, but global interconnect energy and delay increase
Solution Approach 1:
The patent segments the interconnect into local and global portions, with local interconnect operating at full voltage swing for short distances and global interconnect operating at reduced voltage swing for long distances, optimizing the energy-delay product by assigning different voltage levels to different spatial segments
4Use of energy by moving object
If sub-threshold operation is used, then energy consumption is reduced, but signal swing and noise margin deteriorate
Solution Approach 1:
The patent applies different voltage swing characteristics to different locations in the circuit: full voltage swing is maintained at logic block inputs and outputs where noise margins are critical, while reduced voltage swing is used in the global interconnect where energy consumption is the primary concern, achieving both low power and reliable operation
Data Source
AI summary
A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.