Subthreshold Ratioed Logic Circuit for Stable Ultra-Low Voltage Output
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Solution Overview
Problem
In ultra-low voltage environments, existing logic circuits face challenges with signal integrity, increased logic delay, and high power consumption due to voltage fluctuations and process variations, particularly in subthreshold power supply conditions, leading to unbalanced logic swings and prolonged transition times.
Innovation Solution
A subthreshold ratioed logic circuit comprising a pull-up module, voltage regulation module, and pull-down module, where the pull-up and pull-down modules are connected to control the pull-up current of a PMOS transistor, allowing for quick output of level signals and optimized circuit structure for ultra-low voltage operation, with all modules operating in subthreshold conduction states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate-source voltage VGS is reduced to or below the threshold voltage Vth to achieve ultra-low power consumption, then power consumption is reduced, but the channel current becomes leakage current which is several orders of magnitude smaller than normal operation
Solution Approach 1:
The patent operates MOS transistors in the subthreshold region by setting VGS close to or below Vth, exploiting the exponential relationship between Ileak and VGS to achieve ultra-low power consumption while maintaining functional current through careful parameter optimization
Solution Approach 2:
The circuit dynamically switches between subthreshold conduction for low power and controlled enhancement mode for signal output, using the pull-up/pull-down module configuration to dynamically manage current flow and voltage levels
2Device complexity
If Pseudo-NMOS/PMOS circuit or resistive load circuit is used in ultra-low voltage, then circuit structure is simplified, but the voltage of LOW-LEVEL output becomes much higher than zero resulting in invalid output signal
Solution Approach 1:
The circuit is segmented into separate pull-up and pull-down modules with distinct functions, where the pull-up module provides current source and the pull-down module ensures proper logic level output, resolving the output voltage issue while maintaining structural simplicity
Solution Approach 2:
The pull-down module acts as an intermediary element that actively pulls the output to proper logic levels, compensating for the insufficient pull-up strength in ultra-low voltage conditions and ensuring valid output signals
3Reliability
If current mode or differential logic circuits are used to solve signal integrity, then signal integrity is improved, but voltage reduction becomes difficult and layout complexity increases
Solution Approach 1:
Instead of using complex current mode or differential circuits to achieve signal integrity, the patent inverts the approach by using simple ratioed logic with optimized pull-up/pull-down configuration that naturally provides signal integrity through proper current ratio control
Solution Approach 2:
The patent extracts only the essential elements needed for signal integrity (proper current ratios and voltage levels) from complex current mode circuits, implementing a simplified ratioed logic structure that achieves the same goal without the layout complexity
4Loss of energy
If subthreshold power is supplied, then power consumption is reduced, but voltage fluctuations and process variation have significant impact on logic delay and circuit performance
Solution Approach 1:
The circuit uses feedback mechanisms where the pull-up and pull-down modules are controlled based on output conditions, automatically adjusting current flow to compensate for voltage fluctuations and process variations, maintaining stable logic delay and performance
Solution Approach 2:
The circuit design anticipates the impact of process variations by pre-configuring the pull-up/pull-down current ratios to provide margin and cushioning against performance degradation, ensuring stable operation despite subthreshold voltage fluctuations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables dynamic control of current, reduces power consumption, improves signal transmission speed, and maintains performance in low voltage environments, overcoming bottlenecks in discharge processes and simplifying layout complexity compared to conventional circuits.
Implementation Method 1
the pull-up module, the pull-down module, and the voltage regulation module are all subthreshold conduction states when turned on
Data Source
AI summary
The present disclosure provides a subthreshold ratioed logic circuit and a chip. The subthreshold ratioed logic circuit comprises a pull-up module, a voltage regulation module, a pull-up PMOS transistor and a pull-down module that is turned on or off corresponding to the pull-up module; the first end of the pull-up module is connected to an external circuit, the second end of the pull-up module is connected to the source of the pull-up PMOS transistor, and a power supply, the third end of the pull-up module is connected to the second end of the voltage regulation module; the first end of the voltage regulation module is connected with a compensation adjustment circuit, and the third end of the voltage regulation module is grounded; the drain of the pull-up PMOS transistor connected to the output of the subthreshold ratioed logic circuit.