Self-Aligned Interconnects Using Subtractive Techniques
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Solution Overview
Problem
Current dual-damascene fabrication techniques are inadequate for creating self-aligned interconnect structures at 10 nm Node and smaller feature sizes due to gap fill and resistivity constraints, making it difficult to achieve reliable and efficient on-chip electrical interconnects.
Innovation Solution
The method involves depositing multiple layers of materials followed by subtractive techniques such as dry etching or Atomic Layer Etch to form self-aligned interconnects without filling micro conduits with conductive material, using conductive pillars that extend from a base layer to connect semiconductor device surfaces, allowing for the creation of robust interconnects without voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dual-damascene fabrication techniques are used, then interconnect structures can be formed, but gap fill and resistivity constraints make it impractical for 10 nm Node and smaller feature sizes
Solution Approach 1:
The patent inverts the traditional dual-damascene approach by using subtractive techniques instead of additive filling. Instead of filling trenches with conductive material, the method deposits conformal layers and then selectively removes material to form self-aligned interconnects, thereby avoiding gap fill issues and resistivity problems associated with traditional filling methods at 10 nm Node and below
Solution Approach 2:
The patent changes the fundamental process parameters from additive deposition and CMP to subtractive etching and deposition. This parameter change enables the formation of self-aligned interconnects without the gap fill and resistivity constraints that plague traditional dual-damascene processes at advanced nodes
2Adaptability or versatility
If copper metallization is used, then interconnect technology advances, but CMP processes cause dishing and oxide erosion
Solution Approach 1:
The patent extracts the harmful CMP step from the copper metallization process by using subtractive techniques to form interconnects. Instead of depositing copper and then polishing it (which causes dishing and oxide erosion), the method forms interconnect structures through selective removal of deposited layers, eliminating the harmful effects of CMP
Solution Approach 2:
The patent replaces the mechanical CMP process with a subtractive deposition and etching approach. Instead of using mechanical polishing to remove excess metal, the method uses controlled deposition and selective removal techniques, substituting the mechanical system with a chemical/physical vapor deposition-based system that avoids dishing and oxide erosion
3Productivity
If feature sizes are reduced to 10 nm Node, then device density increases, but traditional patterning techniques become inadequate
Solution Approach 1:
The patent employs self-aligned techniques where previously deposited layers serve as their own masks for subsequent etching steps. This self-service approach eliminates the need for complex alignment and multiple patterning techniques, enabling 10 nm Node fabrication while maintaining ease of manufacture through automated, alignment-free processes
Solution Approach 2:
The patent performs preliminary deposition of conformal layers that automatically define the interconnect geometry before any patterning occurs. This preliminary action of depositing self-aligned structures eliminates the need for traditional lithography alignment at 10 nm Node, simplifying the manufacturing process while achieving high device density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of reliable self-aligned interconnects at 16 nm Node and below, reducing resistivity issues and improving alignment, thereby advancing semiconductor device capabilities.
Implementation Method 1
subtractive techniques such as dry etching or Atomic Layer Etch
Implementation Method 2
subtractive techniques such as dry etching or Atomic Layer Etch
Implementation Method 3
conductive pillars that extend from a base layer to connect semiconductor device surfaces
Data Source
AI summary
A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.