Subword Driver Layout to Suppress GIDL and HEIP Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Leakage currents in semiconductor memory devices, such as DRAM, due to gate-induced drain leakage (GIDL) and hot electron-induced punch-through (HEIP), lead to increased power consumption, which is undesirable in low-power systems.
Innovation Solution
The layout of subword drivers is optimized by increasing the distance between drains and gate electrodes through larger recess regions and narrower center portions, reducing leakage currents by preventing GIDL and HEIP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If subword drivers are provided with relatively low voltages while driving subword lines to non-active potential, then power consumption is reduced, but leakage currents increase due to voltage differences across transistors
Solution Approach 1:
The patent applies preliminary anti-action by introducing a preliminary potential to the source of the transistor before the full voltage difference is applied. This preliminary potential counteracts the formation of large voltage differences that would cause GIDL and HEIP effects, preventing leakage currents before they occur. The source is pre-charged to an intermediate voltage level that reduces the electric field stress across the transistor when the gate and drain are at different potentials.
2Object-generated harmful factors
If relatively high voltage is provided to source of transistor while gate and drain are at high and low voltages respectively, then leakage currents are reduced, but hot electron induced punch-through occurs causing threshold voltage degradation
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the source potential based on the operational state of the transistor. When the transistor is in cutoff mode, the source is maintained at a first potential that prevents HEIP. When the transistor needs to conduct, the source potential is switched to a second potential that enables proper current flow. This dynamic parameter adjustment prevents both GIDL and HEIP effects while maintaining reliable threshold voltage.
3Ease of manufacture
If subword driver layout uses conventional design, then manufacturing is simpler, but leakage currents from GIDL and HEIP increase power consumption
Solution Approach 1:
The patent applies local quality by modifying the layout of specific components within the subword driver circuit, particularly the transistor sources and isolation structures. Instead of changing the entire driver design, only critical regions are modified - the sources are given preliminary potentials and isolated with specific structures. This localized modification reduces leakage currents without significantly complicating the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces leakage currents, thereby minimizing power consumption and improving the performance of semiconductor memory devices.
Implementation Method 1
For example, the relatively low voltage provided to a source of a transistor of the subword driver while a relatively high voltage is provided to a gate of the transistor and a relatively low voltage is provided to the drain of the transistor may result in voltage differences sufficient to induce leakage currents in the transistor. An example of leakage currents may be gate induced drain leakage (GIDL).
Implementation Method 2
For example, the hot electrons are trapped through the SiO2 film and accumulate in the SiN film of the STI. The accumulated hot electrons affect an adjacent transistor's source, and as a result, lower a threshold voltage (Vth) of the adjacent transistor.
Data Source
AI summary
Semiconductor devices including active regions and gate electrodes are disclosed. An example semiconductor device according to the disclosure includes a gate electrode extending in a first direction, and first and second active regions extending in a second direction. The gate electrode has a side extending in the first direction. The first active region includes: a first center portion having a first width in the first direction; and a first end portion disposed at a first end of the first center portion, and having a second width in the first direction that is greater than the first width. The second active region includes: a second center portion having a third width in the first direction. The gate electrode overlaps along the side with portions of the first end portion and the second center portion.