Sulfur-Doped Interfacial Layer for Transistor Interface Quality
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Solution Overview
Problem
As transistor gate lengths shorten, existing integrated circuit devices face challenges in enhancing carrier mobility and reducing interface defects between substrate active regions and gate insulation layers, particularly when using silicon substrates, which limits performance and reliability.
Innovation Solution
Incorporating a sulfur-doped lower insulating layer with a chalcogen element having an atomic weight equal to or greater than 16, such as sulfur, between the active region and the gate insulation layer, along with a passivation layer, to reduce interface defects and improve carrier mobility, while using III-V group materials or germanium for high-performance transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate insulation layer is formed directly on the substrate active region, then the manufacturing process is simple, but interface defects increase and carrier mobility decreases
Solution Approach 1:
The gate insulation layer is segmented into multiple sub-layers: a lower insulating layer (first gate insulation layer) formed directly on the active region, and an upper insulating layer (second gate insulation layer) formed on the lower insulating layer. This segmentation allows each layer to perform specific functions - the lower layer provides interface quality improvement while the upper layer provides insulation, thereby resolving the contradiction between interface quality and manufacturing simplicity.
Solution Approach 2:
The lower insulating layer acts as an intermediary layer between the substrate active region and the upper insulating layer. This intermediate layer mediates the interface between the substrate and the gate insulation structure, reducing interface defects and improving carrier mobility while maintaining the overall insulation function, thus resolving the contradiction between interface quality and structural complexity.
2Productivity
If the gate length is shortened to improve device integration, then productivity increases, but carrier mobility enhancement becomes more difficult
Solution Approach 1:
The invention changes the physical and chemical parameters of the gate insulation layer by using materials with different dielectric constants for the lower and upper insulating layers. The lower insulating layer uses a material with higher dielectric constant to enhance electric field control at the interface, which maintains carrier mobility even when gate length is shortened for higher integration, thus resolving the contradiction between productivity and reliability.
3Reliability
If high-k dielectric materials are used to improve transistor performance, then carrier mobility increases, but interface defects may increase without proper interface treatment
Solution Approach 1:
The lower insulating layer is formed preliminarily on the substrate active region before forming the upper insulating layer. This preliminary action prepares the interface by creating a suitable surface that reduces interface defects, allowing subsequent high-k dielectric materials to be deposited with better interface quality, thus resolving the contradiction between transistor performance enhancement and interface defect reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances carrier mobility, reduces interface defects, and improves the reliability and performance of transistors, particularly in high-voltage and high-reliability applications, by effectively curing surface defects and optimizing electrical characteristics.
Implementation Method 1
a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16
Data Source
AI summary
An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer.