Super-Cell Soft-Bit Reads for Accurate Error Correction
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Solution Overview
Problem
Conventional soft-bit read techniques are limited in applicability to single memory cells and fail to accurately determine the likelihood of errors in super cells, leading to increased bit error rates and reduced storage capacity in memory devices.
Innovation Solution
Performing multi-stage soft-bit read operations on super cells to determine the probability of misreading data bits, providing soft-bit read information for error correction operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional soft-bit read techniques are applied to super cells, then the process can be simplified, but the accuracy of error probability determination deteriorates
Solution Approach 1:
The patent divides the super cell into multiple individual memory cells and performs separate read operations on each cell. By segmenting the super cell reading process into individual cell readings, the system can accurately determine the error probability for each cell while maintaining the ability to handle super cells as a logical unit for storage capacity purposes.
Solution Approach 2:
The patent introduces a new dimension of analysis by reading individual cells within the super cell at different stages. Instead of a single read operation, the system performs multiple reads on individual cells, adding a dimensional aspect to the reading process that enables accurate error probability determination while maintaining super cell functionality.
2Quantity of substance
If storage capacity is increased through super cells, then more data can be stored, but the bit error rate increases
Solution Approach 1:
The patent implements feedback by determining the error probability for each individual cell within the super cell and using this information to guide subsequent read operations. The error probability information is fed back to the system to adjust reading strategies, thereby maintaining reliability even as storage capacity increases through super cell usage.
Solution Approach 2:
The patent changes the parameter of reading approach by transitioning from single-cell reads to multi-cell reads within super cells. By adjusting the reading parameters to accommodate multiple cells and their individual error probabilities, the system maintains reliability while achieving higher storage capacity through super cell implementation.
3Reliability
If multi-stage soft-bit read operations are performed on super cells, then error correction capabilities are improved, but operation time increases
Solution Approach 1:
The patent performs preliminary read operations on individual cells within the super cell to determine error probabilities before the main read operation. By conducting these preliminary actions in advance, the system can optimize subsequent operations and improve error correction capabilities while minimizing the overall time penalty through efficient sequencing of read operations.
Data Source
AI summary
Control logic in a memory device comprising a plurality of memory cells, wherein respective pairs of the memory cells are grouped into super cells to store an odd number of data bits, performs, for each of the odd number of data bits, respective sets of strobe reads on a pair of memory cells that form the at least one super cell and generates soft-bit read information corresponding to the at least one super cell based on combined cell state information obtained from the respective sets of strobe reads. The soft-bit read information can indicate a likelihood of the at least one super cell being misread and can be provided to error correction logic for use in error correction operations.