Super Junction IGBT Trench Structure for Lower Vce and Eoff
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Solution Overview
Problem
Existing insulated gate bipolar transistors (IGBTs) face challenges in reducing both forward voltage drop (Vce) and turn-off power loss (Eoff) simultaneously, as trench gate technology reduces Vce but increases gate charge (Qgc), leading to increased turn-off power loss.
Innovation Solution
A super junction structure is implemented in the IGBT, featuring a higher doping concentration epitaxial layer, trenches with a second conductive type filling layer, and a gate structure that includes a gate dielectric and conductive layer, where the filling layer shields the trench bottom and extracts minority carriers to balance charge and reduce power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If carrier storage technology is applied to reduce forward voltage drop, then conductance modulation effect is improved and forward voltage drop decreases, but device complexity increases
Solution Approach 1:
The doping concentration parameter is changed across different regions of the drift region. By creating a doping concentration gradient from the first drift region (lower concentration) to the second drift region (higher concentration), the device achieves conductance modulation without requiring complex additional structures.
Data Source
AI summary
Provided in the present invention are an insulated gate bipolar transistor with a super junction structure, and a preparation method therefor. The transistor comprises a drift region of a first conduction type, an epitaxial layer, a plurality of trenches arranged at intervals, filling layers of a second conduction type, gate electrode structures, a body region, a body contact region, a source region, an isolation dielectric layer and a source electrode conductive layer, wherein the epitaxial layer is located on an upper surface of the drift region; the filling layers and the gate electrode structures are sequentially arranged in the trenches from bottom to top; each gate electrode structure comprises a gate conductive layer, and a gate dielectric layer, which is located on inner walls of the trench and an upper surface of the filling layer and wrap side walls and a bottom face of the gate conductive layer; the body contact region and the source region are located on an upper surface layer of the body region and are adjacent to an upper surface of the body region; the isolation dielectric layer is provided with a contact hole, which penetrates the isolation dielectric layer and exposes the source region and the body contact region; and the source electrode conductive layer fills the contact hole and covers the isolation dielectric layer. In the present invention, the filling layer is formed at the bottom of each trench so as to shield the overlapping area between the bottom of the trench and the drift region, thereby reducing gate electrode charges Qgc.