Super Junction MOSFET JFET Layout for Gate Voltage Stability
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Solution Overview
Problem
Super junction semiconductor power devices experience significant gate voltage oscillation due to sudden changes in gate-drain capacitance when turned on and off, which affects power conversion efficiency.
Innovation Solution
The design incorporates multiple p-type columns with equal widths and JFET regions of varying widths, allowing for gradual depletion and reduction of gate-drain capacitance changes, thereby reducing oscillation by distributing the sudden change points across multiple source-drain voltage points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If super junction semiconductor power devices are used to reduce on-state resistance and parasitic capacitance, then power conversion efficiency is improved, but gate voltage oscillation becomes severe due to sudden change in gate-drain capacitance
Solution Approach 1:
The patent segments the uniformly spaced p-type columns into multiple groups with different spacing relationships. Specifically, adjacent first p-type columns have a first spacing, while adjacent second p-type columns have a second spacing that differs from the first spacing. This segmentation causes the JFET regions to deplete at different voltage points, distributing the gate-drain capacitance change across multiple stages rather than occurring suddenly, thereby reducing gate voltage oscillation while maintaining low switching loss.
2Ease of manufacture
If uniform spacing between p-type columns is used, then manufacturing is simplified, but gate-drain capacitance changes suddenly causing voltage oscillation
Solution Approach 1:
The patent divides the p-type columns into at least two groups (first and second p-type columns) with different spacing characteristics. The first group has a first spacing between adjacent columns, while the second group has a second spacing that is different from the first spacing. This segmented approach allows the device to avoid sudden gate-drain capacitance changes while maintaining manufacturability through systematic rather than random spacing variations.
Solution Approach 2:
The patent applies different spacing characteristics to different groups of p-type columns. Specifically, adjacent first p-type columns have a first spacing, while adjacent second p-type columns have a second spacing. This local differentiation in spacing creates regions with different depletion characteristics, causing the gate-drain capacitance to change gradually across multiple voltage points rather than suddenly, thereby improving gate voltage stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates gate voltage oscillation and enhances power conversion efficiency by smoothing the capacitance transition during switching, improving the overall performance of super junction semiconductor power devices.
Implementation Method 1
The JFET regions are provided with at least two different widths... reduces the sudden change speed of gate-drain capacitance
Data Source
AI summary
A super junction semiconductor power device includes an n-type drain region, an n-type drift region, multiple p-type columns, a gate structure, and multiple JFET regions. The width of each of the multiple p-type columns is equal. The spacing between two adjacent p-type columns is equal. The tops of the multiple p-type columns are provided with multiple p-type body regions respectively, and the p-type body regions are in one-to-one correspondence with the p-type columns. The widths of the multiple p-type body regions are equal. An n-type source region is provided in each p-type body region. The gate structure is configured to control a current channel between the n-type source region and the n-type drift region to turn on and turn off. The multiple JFET regions are located on the n-type drift region and between adjacent p-type body regions. The multiple JFET regions are provided with at least two different widths.