Semiconductor Super Junction Layout for Low On-Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional vertical diffusion metal-oxide-semiconductor field effect transistors (VDMOSFETs) face limitations in increasing operation voltage due to high on-resistance (Ron) caused by dopant concentration and thickness of the n-type drift doped region, and the multi-epitaxy technology used for super junction structures is costly and complex, making it difficult to reduce device dimensions.
Innovation Solution
A semiconductor device layout structure with a super junction layout unit featuring trenches and doped regions of alternating conductivity types, where the trenches are laterally separated by doped regions, forming a PN junction, which reduces on-resistance and allows for improved voltage withstand without the need for extensive epitaxy processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the dopant concentration and thickness of the n-type drift doped region are increased to improve operation voltage, then the withstand voltage is improved, but the on-resistance increases
Solution Approach 1:
The patent divides the drift region into multiple segments by introducing alternating n-type and p-type doped regions in a super junction structure. This segmentation allows the electric field to be distributed across multiple pn junctions, enabling higher withstand voltage while maintaining lower on-resistance through the combined effect of multiple parallel conduction paths.
Solution Approach 2:
The patent employs a composite doped region structure combining n-type and p-type doped regions in an alternating pattern. This composite structure creates multiple pn junctions that work together to achieve both high breakdown voltage and low on-resistance, resolving the trade-off between these two parameters.
2Reliability
If multi-epitaxy technology is used to fabricate super junction structure, then the dopant concentration of n-type drift doped region can be improved, but the processing steps and fabrication cost increase
Solution Approach 1:
The patent merges the formation of multiple doped regions into a single epitaxial growth process step. By designing the super junction structure to be formed during one epitaxy process rather than requiring separate implantation and diffusion steps for each region, the processing complexity is significantly reduced while maintaining the ability to achieve the desired dopant concentrations.
Solution Approach 2:
The patent performs preliminary doping during the epitaxial growth process itself, incorporating the desired dopant concentrations into the structure as it is being formed. This preliminary action eliminates the need for subsequent complex dopant implantation and thermal diffusion processes that would otherwise be required to achieve the super junction structure.
3Reliability
If multi-epitaxy technology is used to fabricate super junction structure, then the super junction structure can be achieved, but the fabrication cost increases
Solution Approach 1:
The patent combines multiple fabrication operations into a single epitaxial growth process. By forming the super junction structure with alternating n-type and p-type doped regions in one continuous process rather than through multiple separate steps, the fabrication cost is reduced while the super junction structure is successfully achieved.
4Device complexity
If conventional VDMOSFET structure is used, then the fabrication process is simpler, but the device dimensions are hard to reduce
Solution Approach 1:
The patent segments the device structure into a regular pattern of alternating n-type and p-type trenches and doped regions. This segmented layout allows for better space utilization and enables scaling to smaller dimensions while maintaining the electrical performance benefits of the super junction structure. The repetitive pattern facilitates systematic reduction of device dimensions.
Solution Approach 2:
The patent transitions from a planar doping approach to a three-dimensional super junction structure with vertical trenches and alternating doped regions. This dimensional change allows for more efficient use of vertical space, enabling device scaling in the lateral direction while maintaining the electrical characteristics through the vertical super junction architecture.
Data Source
AI summary
A semiconductor device layout structure is provided. The semiconductor device layout structure includes an active region having a first conductivity type over a semiconductor substrate. The active region is provided with semiconductor devices formed thereon. A first super junction layout unit in the active region includes a first trench. A first doped region having a first conductivity type is formed surrounding the first trench. A second trench is formed surrounding the first doped region. A second doped region having a second conductivity type is formed surrounding the second trench. The first trench is laterally separated from the second trench through the first doped region and the second doped region in a plan view.