Super Junction MOSFET Void Control
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Solution Overview
Problem
The formation of voids in p-type semiconductor layers during the manufacturing of super junction structure (SJ) semiconductor devices can lead to instability in MOSFET characteristics due to impurity redistribution and deformation during annealing or heat processing, affecting the breakdown voltage and on-resistance.
Innovation Solution
The semiconductor device design incorporates p-type semiconductor layers with high and low concentration impurity regions, where the impurity concentration decreases towards the void portions, and these voids are intentionally formed and controlled using epitaxial growth conditions to maintain the intended p-type impurity distribution, reducing the impact of void deformation and stabilizing the SJ structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trenches are formed in n-type semiconductor layers and p-type semiconductors are buried in these trenches to provide p-type semiconductor layers, then the super junction structure is formed achieving high breakdown voltage and low on resistance, but void portions are likely to be formed in the p-type semiconductor layers causing instability in MOSFET characteristics
Solution Approach 1:
The patent applies parameter changes by forming a graded buffer layer with gradually varying composition between the semiconductor layer and the insulating layer. The buffer layer contains a composition gradient where the proportion of the first component decreases from the interface with the semiconductor layer toward the insulating layer, while the second component increases correspondingly. This compositional parameter change prevents void formation by reducing lattice mismatch and thermal stress, thereby eliminating the harmful effect of voids on MOSFET characteristic stability while maintaining the high breakdown voltage and low on-resistance properties of the super junction structure.
2Reliability
If p-type semiconductor layers with high concentration impurity regions are used to achieve low on resistance, then electrical current conduction is improved, but impurity redistribution during annealing or heat processing causes characteristic fluctuations
Solution Approach 1:
The patent applies preliminary action by pre-forming the graded buffer layer with controlled composition gradient before the final device fabrication steps. This buffer layer is prepared in advance to establish a stable compositional transition zone that prevents impurity redistribution during subsequent annealing or heat processing steps. The preliminary formation of this compositional gradient structure ensures that the p-type semiconductor layers maintain their intended impurity distribution throughout manufacturing processes, preventing characteristic fluctuations while preserving the low on-resistance property.
3Ease of manufacture
If void portions are formed in p-type semiconductor layers, then the manufacturing process is simplified, but deformation during annealing or heat processing affects breakdown voltage and on-resistance
Solution Approach 1:
The patent applies the blessing in disguise principle by intentionally designing a graded buffer layer that converts the potential harm of composition mismatch into a beneficial stress-gradient structure. Rather than attempting to completely eliminate the buffer layer or voids, the invention utilizes the composition gradient to create a controlled transition zone that accommodates thermal expansion differences and prevents uncontrolled void deformation during heat processing. This approach maintains manufacturing simplicity while ensuring that any voids formed do not degrade device performance, thereby preserving both ease of manufacture and breakdown voltage characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains the p-type impurity distribution and enhances the stability of MOSFET characteristics by minimizing the change in impurity concentration, thereby achieving higher breakdown voltage and reducing the susceptibility to characteristic fluctuations.
Implementation Method 1
these voids are intentionally formed and controlled using epitaxial growth conditions to maintain the intended p-type impurity distribution
Data Source
AI summary
A semiconductor device of an embodiment has a first conductive type first semiconductor layer, a second conductive type second semiconductor layer provided in the first semiconductor layer having a first lateral surface and a first bottom portion contacting the first semiconductor layer. The second semiconductor layer has a first void portion inside. A second conductive type impurity concentration decreases from the first lateral surface toward the first void portion. And the device has a second conductive type third semiconductor layer provided in the first semiconductor layer such that the first semiconductor layer is sandwiched between the third semiconductor layer and the second semiconductor layer. The third semiconductor layer has a second lateral surface and a second bottom portion contacting the first semiconductor layer. The third semiconductor layer has a second void portion inside. A second conductive type impurity concentration decreases from the second lateral surface toward the second void portion.