Superconducting Quantum Circuits With Low-Power Multilayer Fabrication
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Solution Overview
Problem
Existing superconducting integrated circuits face challenges in operating at ultralow mK temperatures with reduced power dissipation and enhanced quantum coherence, particularly in quantum computing applications, where scaling and integration with classical circuits are necessary while minimizing defects and fluctuations.
Innovation Solution
The solution involves using silicon nitride as insulating layers, reducing Josephson junction critical current, incorporating a high-kinetic-inductance layer, employing a non-superconducting resistive layer, and utilizing deuterium to minimize hydrogen contamination, along with advanced planarization techniques to enhance coherence and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate fabrication processes are used for different circuit components, then design flexibility is maintained, but manufacturing complexity and time increase
Solution Approach 1:
The patent combines multiple separate fabrication processes into a single integrated process that simultaneously patterns multiple circuit components (qubit circuits, resonator circuits, transmission line circuits) on the same substrate. This is achieved through a unified lithography and etching sequence that defines all circuit features in one manufacturing run, thereby reducing manufacturing complexity while preserving design flexibility through configurable layout parameters.
Solution Approach 2:
The fabrication process is designed to be universal, accommodating different circuit component types and configurations within a single process flow. The method can fabricate various qubit architectures (transmon, flux, phase), different resonator types, and multiple circuit layouts using the same fundamental process steps, eliminating the need for component-specific process variations.
2Manufacturing precision
If separate fabrication processes are used for different circuit components, then individual optimization is possible, but fabrication time increases
Solution Approach 1:
The methodology performs preliminary design optimization by allowing individual circuit components to be designed and simulated separately before integration into the unified fabrication process. This enables optimization of each component's performance parameters while ensuring compatibility with the overall circuit architecture, and the optimized designs are then implemented in a single manufacturing step.
Solution Approach 2:
Multiple fabrication operations that would otherwise be performed sequentially are merged into a single simultaneous process. The lithography step patterns all circuit components in one exposure, and the etching process defines all features in one treatment, thereby maintaining individual component optimization while reducing total fabrication time significantly.
3Ease of manufacture
If conventional lithography is used, then existing equipment can be utilized, but feature size limitations prevent smaller components
Solution Approach 1:
The patent changes the key parameter of lithographic resolution by transitioning from conventional optical lithography to electron beam lithography. This parameter change enables the fabrication of much smaller feature sizes (sub-micron scale) necessary for advanced quantum circuit components, while the methodology remains compatible with standard semiconductor fabrication equipment and processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced power dissipation and increased quantum coherence, enabling the fabrication of scalable superconducting circuits suitable for quantum computing with improved performance and compatibility with classical circuits.
Implementation Method 1
An electron beam is used to write patterns of superconducting circuit geometry
Implementation Method 2
An ion beam is used to expose regions for etching
Implementation Method 3
The methods described herein provide an improved route to quantum integrated circuits (QICs) by fabricating qubit circuits, resonator circuits, and transmission line circuits on the same substrate... at cryogenic temperatures
Data Source
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AI summary
Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/µm2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.