Superconducting TSV Interconnect Groove Layout for Reliable Chip Stacking
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Solution Overview
Problem
The existing methods for forming through silicon via interconnection structures in superconducting quantum devices face challenges in reliably connecting superconducting thin films on the surface of a silicon wafer to those within the via due to poor spin coating effects, leading to etching issues and unreliable connections between chips.
Innovation Solution
A method involving photolithography to create a groove communicating with the through silicon via, followed by depositing superconducting thin films in the groove and via using ALD or CVD processes, ensuring reliable connections without subsequent photolithography on the thin films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography process is used to form superconducting thin film pattern on silicon wafer surface, then circuit structure can be formed, but superconducting thin film near through silicon via is etched away due to poor spin coating effect
Solution Approach 1:
The patent applies preliminary action by forming the groove structure in the silicon wafer before depositing the superconducting thin film. This pre-formed groove provides a physical guide and containment structure that ensures the superconducting material is properly positioned and connected to the through silicon via, eliminating the need for subsequent photolithography etching that would compromise the thin film.
Solution Approach 2:
The patent segments the formation process into distinct stages: first forming the groove structure, then depositing the superconducting thin film. This segmentation allows each process to be optimized independently, with the groove formation enabling reliable material placement without requiring high-precision photolithography in the subsequent thin film formation step.
2Ease of manufacture
If spin coating process is used in photolithography, then photoresist can be applied, but poor spin coating effect occurs near through silicon via leading to etching issues
Solution Approach 1:
The groove is formed preliminarily before photoresist application, creating a physical structure that guides the spin coating process. The groove confines the photoresist material, ensuring uniform coating even in the challenging area near the through silicon via, thereby eliminating the spin coating defects that would otherwise occur.
3Ease of manufacture
If superconducting thin film is deposited and then photolithography is performed, then circuit pattern can be formed, but subsequent photolithography causes etching of the thin film
Solution Approach 1:
The patent inverts the conventional sequence by forming the groove structure first, then depositing the superconducting thin film. This inversion eliminates the need for subsequent photolithography etching of the thin film, as the groove already defines the desired pattern and the thin film can be deposited directly into the groove without requiring chemical etching steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach avoids etching of superconducting thin films near the via, eliminating impurities and oxide layers, thereby ensuring reliable connections and improved signal transmission between stacked chips.
Implementation Method 1
forming a groove communicating with the through silicon via in a target surface of the first surface and the second surface of the silicon wafer using a photolithography process
Implementation Method 2
forming superconducting thin films in a surface of the silicon wafer and in the through silicon via by using an Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process
Implementation Method 3
forming superconducting thin films in a surface of the silicon wafer and in the through silicon via by using an Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process
Data Source
AI summary
A through silicon via interconnection structure and a method of forming same, and a quantum computing device are provided. The method includes: providing a silicon wafer, having a first surface and a second surface opposite to each other; forming, in the silicon wafer, a through silicon via penetrating through the silicon wafer in a direction from the first surface to the second surface of the silicon wafer; forming a groove communicating with the through silicon via in a target surface of the first surface and the second surface of the silicon wafer using a photolithography process; and forming a superconducting thin film in the groove and the through silicon via to obtain the through silicon via interconnection structure.