Superdie Memory Die Testing With Shared Probe Signals
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Solution Overview
Problem
Conventional memory die testing methods become inefficient and costly as die sizes decrease and spacing between dies on a wafer narrows, leading to increased testing time and complexity due to alignment issues with probe cards.
Innovation Solution
Merging two or more memory dies into a 'superdie' allows concurrent testing using a single set of micro-probes, with shared power and control signals, and separating dies post-testing for individual use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory die testing methods are used with decreasing die sizes and narrower spacing, then manufacturing density increases, but testing time and complexity increase due to alignment issues with probe cards
Solution Approach 1:
The patent merges multiple memory dies (first die and second die) into a single testable unit by electrically connecting corresponding pads between the dies. This allows the probe card to test both dies simultaneously through a single set of probes, effectively combining multiple test targets into one unified testing operation.
Solution Approach 2:
The patent creates a universal testing approach where a single set of probe card contacts can serve multiple memory dies concurrently. The shared power pads and control pads enable one probe card to perform testing functions for both the first and second memory dies, making the testing system multi-functional rather than requiring separate probe sets for each die.
2Quantity of substance
If conventional memory die testing methods are used with decreasing die sizes and narrower spacing, then manufacturing density increases, but device complexity increases due to alignment issues with probe cards
Solution Approach 1:
The patent merges multiple memory dies (first die and second die) into a single testable unit by electrically connecting corresponding pads between the dies. This allows the probe card to test both dies simultaneously through a single set of probes, effectively combining multiple test targets into one unified testing operation.
Solution Approach 2:
The patent creates a universal testing approach where a single set of probe card contacts can serve multiple memory dies concurrently. The shared power pads and control pads enable one probe card to perform testing functions for both the first and second memory dies, making the testing system multi-functional rather than requiring separate probe sets for each die.
3Measurement precision
If multiple separate probe cards are used to test each die individually, then testing precision is maintained, but testing time and cost increase
Solution Approach 1:
The patent merges multiple memory dies (first die and second die) into a single testable unit by electrically connecting corresponding pads between the dies. This allows the probe card to test both dies simultaneously through a single set of probes, effectively combining multiple test targets into one unified testing operation.
Solution Approach 2:
The patent creates a universal testing approach where a single set of probe card contacts can serve multiple memory dies concurrently. The shared power pads and control pads enable one probe card to perform testing functions for both the first and second memory dies, making the testing system multi-functional rather than requiring separate probe sets for each die.
Data Source
AI summary
A semiconductor wafer includes a plurality of memory dies disposed thereon. The plurality of memory dies are arranged as a plurality of superdies for testing, wherein each of the plurality of superdies comprises two or more of the plurality of memory dies. At least a subset of components of the two or more of the plurality of memory dies in each of the plurality of superdies are electrically shorted together to receive shared test signals from test equipment during the testing.