Superlattice DMOS Drift Region With Field Plate Depletion
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Solution Overview
Problem
Current semiconductor devices face limitations in achieving enhanced charge carrier mobility and performance due to issues like alloy scattering, sub-stoichiometric insulating properties, and unwanted scattering effects at interfaces.
Innovation Solution
The implementation of a double-diffused metal oxide semiconductor (DMOS) device with a superlattice structure, comprising stacked groups of semiconductor and non-semiconductor monolayers, which reduces effective mass, improves interface quality, and acts as a barrier to dopant diffusion, thereby enhancing charge carrier mobility and providing piezoelectric, pyroelectric, and ferroelectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a superlattice structure is implemented to enhance charge carrier mobility, then scattering effects are reduced and mobility is improved, but device complexity increases due to the multi-layer structure
Solution Approach 1:
The drift region is segmented into multiple alternating layers of semiconductor material (e.g., silicon) and non-semiconductor material (e.g., silicon oxide or silicon nitride), forming a superlattice structure. Each layer is thin (e.g., 1-10 nm), creating a periodic structure that segments the drift region into multiple quantum wells. This segmentation reduces alloy scattering and phonon scattering, thereby enhancing charge carrier mobility while maintaining a manageable device architecture through repetitive patterning.
Solution Approach 2:
The patent employs composite materials by combining semiconductor materials (such as silicon or silicon-germanium) with non-semiconductor materials (such as silicon oxide or silicon nitride) to form the superlattice structure. This composite approach allows the drift region to exhibit both high carrier mobility (from the semiconductor layers) and appropriate insulating properties (from the non-semiconductor layers), resolving the contradiction between mobility enhancement and device complexity through material composition rather than structural complexity alone.
2Reliability
If the drift region is depleted to improve device performance, then breakdown voltage is enhanced, but on-resistance increases
Solution Approach 1:
The superlattice structure introduces local quality variations within the drift region through alternating semiconductor and non-semiconductor layers. The semiconductor layers provide high carrier mobility channels, while the non-semiconductor layers provide localized insulation and field control. This local differentiation allows the drift region to achieve both high breakdown voltage (through adequate depletion in non-semiconductor regions) and low on-resistance (through high-mobility paths in semiconductor regions), resolving the contradiction between reliability and power efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DMOS device with a superlattice structure achieves higher charge carrier mobility by reducing scattering effects, improving interface quality, and confining carriers effectively, leading to enhanced performance and tailored band structures suitable for various electronic and opto-electronic devices.
Implementation Method 1
U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si—Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice
Implementation Method 2
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Implementation Method 3
U.S. Pat. No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer
Implementation Method 4
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Implementation Method 5
a field plate layer adjacent the drift region and configured to deplete the drift region
Implementation Method 6
U.S. Pat. No. 7,105,895 to Wang et al. discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude
Data Source
AI summary
A double-diffused MOS (DMOS) device may include a semiconductor layer having a first conductivity type, a drift region of a second conductivity type in the semiconductor substrate, spaced-apart source and drain regions in the semiconductor layer, and a first superlattice on the semiconductor layer. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a gate above the first superlattice, and a field plate layer adjacent the drift region and configured to deplete the drift region.