Superlattice Punch-Through Stop Layers for Vertical Fin Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face limitations in enhancing charge carrier mobility and integrating advanced materials effectively, despite previous advancements in strained layers and superlattice structures.
Innovation Solution
The development of a semiconductor device method involving superlattices with stacked groups of semiconductor and non-semiconductor monolayers, where the non-semiconductor monolayers are constrained within the crystal lattice of adjacent semiconductor portions, forming punch-through stop layers and enhancing conductivity effective masses for improved mobility and reduced dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor structures are used, then manufacturing is simpler, but charge carrier mobility is limited
Solution Approach 1:
The semiconductor structure is divided into multiple thin monolayer layers (semiconductor and non-semiconductor alternating layers) to form a superlattice. This segmentation creates multiple interfaces that generate piezoelectric fields, enhancing charge carrier mobility through reduced scattering and improved transport properties without requiring excessive structural complexity.
Solution Approach 2:
The patent employs composite material structures combining semiconductor monolayers (e.g., GaAs, AlAs) with non-semiconductor monolayers to create superlattices. These composite structures exhibit enhanced electrical properties including improved charge carrier mobility, reduced scattering, and emergent piezoelectric, pyroelectric, and ferroelectric characteristics.
2Reliability
If dopant diffusion is not controlled, then manufacturing is easier, but device performance degrades
Solution Approach 1:
Punch-through stop layers are formed preliminarily within the superlattice structure before final device assembly. These stop layers pre-establish boundaries that control dopant diffusion pathways, preventing unwanted dopant migration into active regions and ensuring reliable device performance from the outset.
Solution Approach 2:
The superlattice structure acts as an intermediary layer between dopant sources and active device regions. The alternating semiconductor and non-semiconductor monolayers create a barrier that mediates dopant diffusion, allowing controlled dopant distribution while maintaining device performance through reduced scattering and improved carrier transport.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher charge carrier mobility, reduced scattering effects, and enhanced device performance, including piezoelectric, pyroelectric, and ferroelectric properties, suitable for various semiconductor devices.
Implementation Method 1
enhanced device performance, including piezoelectric, pyroelectric, and ferroelectric properties
Implementation Method 2
The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.