Superpage Allocation for Stack Memory TLB Miss Reduction
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Solution Overview
Problem
Modern processors face significant time penalties due to translation lookaside buffer (TLB) misses, which can be exacerbated by stack growth causing page faults, and existing solutions require extensive hardware redesign or are limited in their ability to optimize memory usage.
Innovation Solution
Implementing the use of superpages in page table and TLB entries for stack memory allocation, allowing for automatic creation of superpages in the page table and TLB to prevent costly TLB misses and page faults, with superpages referencing larger portions of memory than normal size pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal size pages are used for stack memory allocation, then hardware complexity is low, but TLB misses and page faults increase significantly
Solution Approach 1:
The patent changes the parameter of page size from normal size to superpage size (e.g., 4KB to 2MB) for stack memory allocation. This parameter change allows fewer TLB entries to cover the same address space, reducing TLB misses. The page table structure is modified to support variable page sizes, with superpages indicated by a special bit in the page table entry.
Solution Approach 2:
The patent implements dynamic page size selection where the system can choose between normal pages and superpages based on memory access patterns. The page table structure allows flexible configuration where each page table entry can specify whether it maps to a normal page or a superpage, enabling adaptive optimization without requiring complete hardware redesign.
2Productivity
If superpages are used to reduce TLB misses, then TLB performance improves, but page fault handling complexity increases
Solution Approach 1:
The patent implements self-service page fault handling by using the existing page table structure and TLB mechanisms to manage superpages. The operating system automatically creates superpages when needed, and the hardware TLB naturally handles translations without requiring special intervention. The page table entry format is extended with a single bit to indicate superpage status, allowing the existing fault handling infrastructure to work with minimal modification.
3Ease of manufacture
If fixed page size is used, then hardware implementation is simple, but memory allocation efficiency decreases
Solution Approach 1:
The patent introduces dynamic page size support while maintaining backward compatibility with fixed page size implementations. The page table structure includes an optional bit that can be ignored in fixed-size systems, allowing gradual adoption. This enables systems to benefit from superpage efficiency where applicable while maintaining simplicity in environments where fixed sizing is preferred.
Solution Approach 2:
The patent segments the address space into different page size categories (normal pages and superpages) within the same memory management framework. This segmentation allows flexible memory allocation strategies where superpages can be used for large contiguous allocations like stacks, while normal pages handle smaller allocations, optimizing overall memory usage efficiency.
Data Source
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AI summary
In one embodiment, the present invention includes a page fault handler to create page table entries and TLB entries in response to a page fault, the page fault handler to determine if a page fault resulted from a stack access, to create a superpage table entry if the page fault did result from a stack access, and to create a TLB entry for the superpage. Other embodiments are described and claimed.