Suppressing Mis-predicted Control Transfer Instructions
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Solution Overview
Problem
In modern out-of-order processors, branch predictor corruption occurs due to mispredicted control transfer instructions, leading to performance losses and inaccurate updates, especially in multi-threaded environments where younger control transfer instructions on mispredicted paths can degrade branch predictor accuracy and cause spurious instruction flushes.
Innovation Solution
A mechanism that suppresses the results of younger control transfer instructions on mispredicted speculative execution paths, using a misprediction bit to prevent pipeline flushes and incorrect updates to the branch predictor, ensuring that only non-speculative control transfer instructions from other threads can update the predictor and redirect the instruction fetch unit to the correct path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the branch predictor is updated with results of every control transfer instruction to enhance future prediction accuracy, then branch predictor accuracy is improved, but younger CTIs on mispredicted speculative execution paths corrupt the branch predictor and cause spurious flushes
Solution Approach 1:
The patent segments the control transfer instructions into two categories: those on correct execution paths and those on mispredicted speculative paths. By introducing a misprediction bit that segments the processing logic, the system updates the branch predictor only for CTIs on correct paths while suppressing updates from CTIs on mispredicted paths, thus resolving the contradiction between updating for accuracy and preventing corruption
Solution Approach 2:
The misprediction bit acts as an intermediary mechanism between CTI execution and branch predictor updates. This intermediary suppresses harmful updates from younger CTIs on mispredicted paths while allowing beneficial updates from CTIs on correct paths, thereby maintaining branch predictor fidelity without sacrificing prediction accuracy
2Productivity
If younger CTIs on mispredicted paths are allowed to execute and update the branch predictor, then execution throughput is maintained, but spurious pipeline flushes occur and performance is degraded
Solution Approach 1:
The patent converts the potentially harmful effect of younger CTIs on mispredicted paths into a beneficial filtering mechanism. By using the misprediction bit to identify and suppress these CTIs, the system prevents spurious flushes and performance degradation while maintaining throughput from valid CTIs, thus transforming a problem into a solution
3Productivity
If multiple threads are executed concurrently on CMT processors, then overall processor performance is improved, but CTIs from different threads interleave and cause execution order confusion
Solution Approach 1:
The patent applies segmentation by associating a dedicated misprediction bit with each execution thread. This per-thread misprediction bit allows independent tracking and suppression of younger CTIs on mispredicted paths for each thread, managing the complexity of interleaved CTIs from multiple threads while maintaining high processor performance
Data Source
AI summary
Techniques are disclosed relating to a processor that is configured to execute control transfer instructions (CTIs). In some embodiments, the processor includes a mechanism that suppresses results of mispredicted younger CTIs on a speculative execution path. This mechanism permits the branch predictor to maintain its fidelity, and eliminates spurious flushes of the pipeline. In one embodiment, a misprediction bit is be used to indicate that a misprediction has occurred, and younger CTIs than the CTI that was mispredicted are suppressed. In some embodiments, the processor may be configured to execute instruction streams from multiple threads. Each thread may include a misprediction indication. CTIs in each thread may execute in program order with respect to other CTIs of the thread, while instructions other than CTIs may execute out of program order.