Surrounding-Gate IGZO TFT Selector for Dense BEOL Memory Cells
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Solution Overview
Problem
The size limitation of CMOS transistors is a bottleneck for improving the size and memory cell density in emerging memory technologies such as MRAM, RRAM, FeRAM, and PCM, as they are used as selecting transistors.
Innovation Solution
Employing surrounding gate thin film transistors (TFTs), specifically Indium-Gallium-Zinc-Oxide (IGZO) TFTs, as selecting transistors to form memory cell selectors, which are processed at low temperatures and integrated in the back-end-of-line (BEOL) fabrication, allowing for higher memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS transistors are used as selecting transistors in memory cell elements, then the device can operate reliably, but the transistor size cannot be reduced further which limits memory cell density
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional CMOS to oxide semiconductor (IGZO), enabling smaller transistor sizes while maintaining reliable operation. This material parameter change allows the transistor to achieve both miniaturization and sustained reliability, resolving the contradiction between size reduction and operational reliability.
Solution Approach 2:
The patent employs composite material structures including oxide semiconductor channels combined with specific gate dielectric materials and electrode materials. This composite approach enables the transistor to achieve superior electrical characteristics and reliability at reduced sizes, overcoming the limitations of conventional CMOS transistors.
2Quantity of substance
If transistor size is reduced to increase memory cell density, then areal density improves, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
By changing to oxide semiconductor materials, the patent enables fabrication of smaller transistors with maintained precision through material properties that are more tolerant to manufacturing variations. The oxide semiconductor material allows for reduced feature sizes while preserving manufacturing feasibility and precision.
Solution Approach 2:
The patent replaces conventional CMOS fabrication processes with oxide semiconductor processing techniques that enable smaller feature sizes. The material substitution allows for reduced transistor dimensions while maintaining manufacturing precision through different processing mechanisms that are better suited for miniaturization.
3Area of stationary object
If peripheral transistors are moved from FEOL to BEOL, then chip area is freed in FEOL, but processing temperature must be low to avoid damaging existing devices
Solution Approach 1:
The patent changes the processing temperature parameter by using oxide semiconductor materials that can be fabricated at lower temperatures. This material parameter change enables BEOL integration of transistors without damaging previously fabricated devices, while still achieving the desired area optimization by relocating peripheral transistors.
Data Source
AI summary
A memory structure, device, and method of making the same, the memory structure including: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; a gate electrode surrounding the high-k dielectric layer; and a memory cell electrically connected to the drain electrode and a bit line. The memory cell includes a first electrode that is electrically connected to the drain electrode.